Digital predistortion system and method for correcting memory effects within an RF power amplifier

• US 20050001684A1
• Filed: 06/30/2004
• Published: 01/06/2005
• Est. Priority Date: 07/03/2003
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Powerwave Technologies Incorporated
• Inventors: Braithwaite, Richard Neil
• Granted Patent: US 7,149,257 B2
• Time in Patent Office: Days
• US Class Current: 330/263
• CPC Class Codes: H03F 1/3247 using feedback acting on predistortion circuits H03F1/3264 takes precedence
• CPC Class Codes: H03F 2201/3224 Predistortion being done for compensating memory effects
• CPC Class Codes: H03F 2201/3233 Adaptive predistortion using lookup table, e.g. memory, RAM, ROM, LUT, to generate the predistortion

Abstract

A system and method of correcting memory effects present within power amplifiers using digital predistortion and an improved power amplifier system employing digital predistortion are disclosed. Nonlinearities within a power amplifier having an input derived from a digital signal are compensated by injecting a digital correction signal prior to the power amplifier. A system and method for modeling the distortion created by power amplifier memory effects and generating the desired digital predistortion correction signal are disclosed.

Claims

1. A digital predistorter adapted to receive a digital input signal and output a predistorted digital signal, the digital predistorter comprising:

an input coupled to receive the digital input signal;

a first signal path coupled to the input and comprising a delay circuit and a combiner circuit coupled to the output of the delay circuit;

a second signal path, coupled to the input in parallel with said first signal path, comprising a first digital predistorter circuit providing a first predistortion operation on the input signal; and

a third signal path, coupled to the input in parallel with said first and second signal path, comprising a second digital predistorter circuit providing a second different predistortion operation on the input signal;

wherein the combiner circuit receives and combines the outputs of the first and second digital predistorter circuits with the output of the delay circuit of the first signal path to provide a predistorted digital output signal.

2. A digital predistorter as set out in claim 1, wherein said first digital predistorter circuit provides said first predistortion operation modeling memoryless distortion effects employing only a current sample of the digital input signal.

3. A digital predistorter as set out in claim 2, wherein said second digital predistorter circuit provides said second predistortion operation modeling memory distortion effects employing plural samples of the digital input signal.

4. A digital predistorter as set out in claim 1, wherein said combiner circuit comprises a complex addition circuit.

5. A digital predistorter as set out in claim 1, further comprising a second combiner circuit coupled to the outputs of the first and second digital predistorter circuits and providing a combined output of the first and second digital predistorter circuits to the combiner circuit in the first signal path.

6. A digital predistorter as set out in claim 5, wherein said second combiner circuit comprises a complex addition circuit.

7. A digital predistortion circuit adapted to receive a digital input signal and output a digital predistortion correction signal compensating for memory effects due to plural samples of the input signal, the digital predistortion circuit comprising:

an input for receiving the digital input signal;

a first signal path comprising a delay circuit coupled to the input and a combiner circuit coupled to the output of the delay circuit;

a filter bank, coupled to the input and configured in parallel with the first signal path, the filter bank comprising at least two filters having different frequency responses and outputting at least first and second band limited signals derived from plural samples of the digital input signal; and

a plurality of nonlinear operation circuits coupled to the filter bank and receiving the band limited signals, the nonlinear operation circuits creating higher order signals from the band limited signals;

wherein the outputs of the nonlinear operation circuits are provided to the combiner circuit in the first signal path and combined with the delayed input signal output from the delay circuit in the first signal path to provide a digital predistortion output signal.

8. A digital predistortion circuit as set out in claim 7, further comprising a plurality of weighting circuits coupled to the outputs of the nonlinear operation circuits and applying respective weighting coefficients to the higher order signals.

9. A digital predistortion circuit as set out in claim 8, wherein the input signal has an associated frequency bandwidth, wherein one or more of the higher order signals fall within the bandwidth of the input signal, and wherein the weighting coefficients apply a selective weighting for the one or more higher order signals within the bandwidth of the input signal.

10. A digital predistortion circuit as set out in claim 7, wherein said combiner circuit is a complex multiplication circuit and wherein the predistortion output signal output from the combiner circuit is a third order signal derived from the input signal and the higher order signals from the nonlinear operation circuits.

11. A digital predistortion circuit as set out in claim 7, further comprising a plurality of complex addition circuits receiving and adding the higher order signals from the plurality of nonlinear operation circuits and providing the combined higher order signals to the combiner circuit in the first signal path.

12. A digital predistortion circuit as set out in claim 7, wherein said filter bank comprises first and second filters having a first fixed frequency response and a second fixed frequency response, respectively, the second frequency response comprising the image of the first frequency response.

13. A digital predistortion circuit as set out in claim 12, wherein said plurality of nonlinear operation circuits comprises:

a first nonlinear operation circuit comprising a first complex conjugation circuit receiving the output of the second filter and a first complex multiplication circuit receiving the output of the first complex conjugation circuit and the output of the first filter and providing a first higher order signal;

a second nonlinear operation circuit comprising first and second magnitude squared circuits receiving the outputs of the first and second filter, respectively, and an addition circuit adding the outputs of the first and second magnitude squared circuits and providing the output as a second higher order signal; and

a third nonlinear operation circuit comprising a second complex conjugation circuit receiving the output of the first filter and a second complex multiplication circuit multiplying the output of the second complex conjugation circuit and the output of the second filter to provide a third higher order signal.

14. A digital predistortion circuit adapted to receive a digital input signal and output a digital predistortion signal compensating for memory effects due to plural samples of the input signal, the digital predistortion circuit comprising:

an input for receiving the digital input signal;

a first signal path comprising a delay circuit coupled to the input and a combiner circuit coupled to the output of the delay circuit;

a nonlinear operation circuit coupled to the input and configured in parallel with the first signal path and receiving the digital input signal, the nonlinear operation circuit creating a higher order signal from the digital input signal; and

a filter bank, coupled to the nonlinear operation circuit and receiving the higher order signal, the filter bank comprising plural filters having different frequency responses and outputting plural band limited higher order signals derived from plural samples of the higher order signal;

wherein the outputs of the filters are provided to the combiner circuit in the first signal path and combined with the delayed input signal output from the delay circuit in the first signal path to provide a digital predistortion output signal.

15. A digital predistortion circuit as set out in claim 14, wherein said input signal is a complex signal and wherein said nonlinear operation circuit comprises a magnitude squared circuit providing a signal corresponding to the magnitude squared of the complex digital input signal.

16. A digital predistortion circuit as set out in claim 14, further comprising a plurality of weighting circuits coupled to the outputs of the plurality of filters and applying respective weighting coefficients to the band limited higher order signals.

17. A digital predistortion circuit as set out in claim 16, wherein the input signal has an associated frequency bandwidth, wherein one or more of the band limited higher order signals fall within the bandwidth of the input signal, and wherein the weighting coefficients apply a selective weighting for the one or more higher order signals within the bandwidth of the input signal.

18. A digital predistortion circuit as set out in claim 14, wherein said combiner circuit is a complex multiplication circuit and wherein the predistortion output signal output from the combiner circuit is a third order signal derived from the input signal and the band limited higher order signals.

19. A digital predistortion circuit as set out in claim 14, further comprising a plurality of complex addition circuits receiving and adding the band limited higher order signals and providing the combined band limited higher order signals to the combiner circuit in the first signal path.

20. A digital predistortion circuit as set out in claim 14, wherein said filter bank comprises first and second filters having a first fixed frequency response and a second fixed frequency response, respectively, the second frequency response comprising the image of the first frequency response, and a third filter having a different frequency response than said first and second filters.

21. A digital predistortion circuit adapted to receive a digital input signal and output a digital predistortion signal compensating for memory effects due to plural samples of the input signal, the digital predistortion circuit comprising:

an input for receiving the digital input signal;

a filter bank comprising at least two filters having different frequency responses and outputting at least first and second band limited signals derived from plural samples of the digital input signal;

a plurality of nonlinear operation circuits coupled to the filter bank and receiving the band limited signals, the nonlinear operation circuits creating third order or higher order signals from the band limited signals; and

one or more combiner circuits receiving and combining the outputs of the nonlinear operation circuits to provide a digital predistortion output signal.

22. A digital predistortion circuit as set out in claim 21, further comprising a plurality of weighting circuits coupled to the outputs of the nonlinear operation circuits and applying respective weighting coefficients to the higher order signals.

23. A digital predistortion circuit as set out in claim 22, wherein the input signal has an associated frequency bandwidth, wherein one or more of the higher order signals fall within the bandwidth of the input signal, and wherein the weighting coefficients apply a selective weighting for the one or more higher order signals within the bandwidth of the input signal.

24. A digital predistortion circuit as set out in claim 21, wherein said one or more combiner circuits comprise a plurality of complex addition circuits.

25. A digital predistortion circuit as set out in claim 21, wherein said filter bank comprises first and second filters having a first fixed frequency response and a second fixed frequency response, respectively, the second frequency response comprising the image of the first frequency response.

26. A digital predistortion circuit as set out in claim 25, wherein said plurality of nonlinear operation circuits comprises:

a first nonlinear operation circuit comprising a first complex squaring circuit receiving the output of the first filter, a first conjugation circuit receiving the output of the second filter, and a first complex multiplication circuit receiving the output of the complex squaring circuit and the first complex conjugation circuit and providing a first higher order signal;

a second nonlinear operation circuit comprising first and second magnitude squared circuits receiving the outputs of the first and second filter, respectively, an addition circuit adding the outputs of the first and second magnitude squared circuits, and a second complex multiplication circuit multiplying the output of the first filter and the output of the addition circuit and providing the output as a second higher order signal;

a third nonlinear operation circuit comprising a third complex multiplication circuit receiving and multiplying the output of the second filter and the output of said addition circuit and providing the output as a third higher order signal; and

a fourth nonlinear operation circuit comprising a second complex conjugation circuit receiving the output of the first filter, a second complex squaring circuit receiving the output of the second filter, and a fourth complex multiplication circuit multiplying the output of the second complex conjugation circuit and the output of the second complex squaring circuit to provide a fourth higher order signal.

27. A digital predistortion circuit adapted to receive a digital input signal and output a digital predistortion signal compensating for memory effects due to plural samples of the input signal, the digital predistortion circuit comprising:

an input for receiving the digital input signal;

a nonlinear operation circuit coupled to the input and receiving the digital input signal, the nonlinear operation circuit creating third or higher order signals from the digital input signal;

a filter bank, coupled to the nonlinear operation circuit and receiving the third or higher order signals, the filter bank comprising plural filters having different frequency responses and outputting plural band limited third order or higher order signals derived from plural samples of the third or higher order signal; and

one or more combiner circuits receiving and combining the outputs of the filters to provide a predistortion output signal.

28. A digital predistortion circuit as set out in claim 27, wherein said input signal is a complex signal and wherein said nonlinear operation circuit comprises a circuit providing a third order signal corresponding to the magnitude squared of the complex digital input signal multiplied by the complex digital input signal.

29. A digital predistortion circuit as set out in claim 27, further comprising a plurality of weighting circuits coupled to the outputs of the plurality of filters and applying respective weighting coefficients to the band limited third order or higher order signals.

30. A digital predistortion circuit as set out in claim 29, wherein the input signal has an associated frequency bandwidth, wherein one or more of the band limited third order or higher order signals fall at least partially within the bandwidth of the input signal, and wherein the weighting coefficients apply a selective weighting for the one or more third order or higher order signals within the bandwidth of the input signal.

31. A digital predistortion circuit as set out in claim 27, wherein said one or more combiner circuits comprise a plurality of complex addition circuits receiving and adding the band limited third order or higher order signals.

32. A digital predistortion circuit as set out in claim 27, wherein said filter bank comprises first, second, third and fourth filters each having a different fixed frequency response.

33. An adaptive digital predistortion system adapted to receive a digital input signal and output a predistorted digital signal to a nonlinear component and to receive a digital sample of the output of the nonlinear component, the digital predistortion system comprising:

an input coupled to receive the digital input signal;

a digital predistorter module coupled to the input and comprising a predistortion circuit operating on the digital input signal to create band limited signals from the input signal and employing separate predistortion coefficients for weighting the band limited signals;

an error generator circuit for receiving the digital input signal and the digital sample of the output of the nonlinear component and providing a digital error signal; and

an adaptive coefficient generator coupled to receive the digital input signal and the digital error signal and comprising a spectral weighting circuit to derive separately weighted frequency components from the input signal and error signal and a coefficient estimator circuit for calculating updated predistortion coefficients weighted differently for different frequency components and providing the updated predistortion coefficients to the digital predistorter module.

34. An adaptive digital predistortion system as set out in claim 33, wherein the coefficient estimator circuit comprises a weighted least mean square coefficient estimator.

35. An adaptive digital predistortion system as set out in claim 34, wherein the coefficient estimator circuit comprises a digital signal processor programmed with a weighted least mean square algorithm.

37. An adaptive digital predistortion system as set out in claim 33, wherein the spectral weighting circuit comprises a plurality of digital filters receiving and operating on the digital input signal and the digital error signal.

38. An adaptive digital predistortion system as set out in claim 33, wherein the spectral weighting circuit further comprises a subsequence calculation circuit for deriving frequency limited subsequences from the digital input signal and wherein one of the plurality of digital filters receive and operate on the digital error signal and the remaining ones of the plurality of digital filters receive and operate on the frequency limited subsequences.

39. A linearized amplifier system adapted to receive a digital input signal and output an amplified RF signal, comprising:

an input coupled to receive the digital input signal;

a digital predistorter module comprising a first signal path coupled to the input and comprising a delay circuit and a combiner circuit coupled to the output of the delay circuit, a second signal path coupled to the input in parallel with said first signal path and comprising a first digital predistorter circuit providing a memoryless predistortion operation on the input signal operating on single samples of the input signal, and a third signal path coupled to the input in parallel with said first and second signal paths and comprising a second digital predistorter circuit providing a memory based predistortion operation on the input signal employing plural samples of the input signal, wherein the combiner circuit receives and combines the outputs of the first and second digital predistorter circuits with the output of the delay circuit of the first signal path to provide a predistorted digital signal;

a digital to analog converter coupled to receive the predistorted digital signal from the digital predistorter module and provide a predistorted analog signal;

an up converter receiving the predistorted analog signal from the digital to analog converter and converting it to an RF analog signal; and

a power amplifier receiving the RF analog signal and providing an amplified RF output signal.

40. An adaptively linearized amplifier system, comprising:

an input coupled to receive a digital input signal;

a digital predistorter module coupled to the input and receiving the digital input signal and outputting a predistorted digital signal, the digital predistorter module comprising a predistortion circuit operating on the digital input signal to create band limited signals from the input signal and employing separate predistortion coefficients for weighting the band limited signals;

a digital to analog converter coupled to receive the predistorted digital signal output of the digital predistorter module and provide an analog signal;

an up converter for receiving the analog signal from the digital to analog converter and converting it to an RF analog signal;

a power amplifier receiving the RF analog signal and providing an amplified RF output signal;

an output sampling coupler coupled to sample the analog RF output signal from the power amplifier;

a feedback circuit path, coupled to the output sampling coupler, comprising a down converter and an analog to digital converter converting the sampled RF output signal to a digital sampled signal representative of the RF output signal;

an error generator circuit coupled to the input and the feedback circuit path for receiving the digital input signal and the digital sampled signal and providing a digital error signal; and

an adaptive coefficient generator, coupled to receive the digital input signal and the digital error signal and providing updated predistortion coefficients to the digital predistorter module, comprising a spectral weighting circuit to derive separately weighted frequency components from the digital input signal and digital error signal and a coefficient estimator circuit for calculating updated predistortion coefficients weighted differently for different frequency components.

41. A method for digitally predistorting a digital input signal, comprising:

receiving a digital input signal and splitting the digital input signal along three parallel signal paths;

delaying the signal provided along the first signal path;

digitally predistorting the signal provided along the second signal path employing a single sample of the input signal to provide a memoryless predistortion correction;

digitally predistorting the signal along the third signal path employing plural samples of the input signal to provide a memory based digital predistortion correction; and

combining the memoryless and memory based digital predistortion corrections provided from the second and third signal paths with the delayed signal in the first signal path to provide a predistorted digital output signal.

42. A method for digitally predistorting a digital input signal, comprising:

receiving a digital input signal;

deriving a plurality of band limited higher order signals from the digital input signal;

weighting the plurality of band limited higher order signals with predistortion coefficients varying between the band limited higher order signals to provide a predistortion correction signal; and

combining the predistortion correction signal with the digital input signal to provide a predistorted digital output signal.

43. A method for digitally predistorting a digital input signal as set out in claim 42, wherein deriving a plurality of band limited higher order signals from the digital input signal comprises filtering the input signal to create plural band limited signals and performing plural nonlinear operations on the band limited signals to create said band limited higher order signals.

44. A method for digitally predistorting a digital input signal as set out in claim 42, wherein deriving a plurality of band limited higher order signals from the digital input signal comprises performing a nonlinear operation on the input signal to create a higher order signal and performing plural filtering operations on the higher order signal to create said band limited higher order signals.

45. A method for digitally predistorting a digital input signal as set out in claim 42, wherein said band limited higher order signals are second order signals and wherein said method further comprises multiplying the band limited higher-order signals with the digital input signal to provide a third order digital signal as said predistortion correction signal.

46. A method for digitally predistorting a digital input signal as set out in claim 42, wherein said band limited higher order signals are third order signals.

47. A method for digitally predistorting a digital input signal as set out in claim 42, wherein the input signal has an associated frequency bandwidth, wherein one or more of the band limited higher order signals fall within the frequency bandwidth of the input signal, and wherein the predistortion coefficients apply a selective weighting for the one or more higher order signals within the frequency bandwidth of the input signal.

48. A method for digitally predistorting a digital input signal, comprising:

receiving a digital input signal;

deriving a plurality of higher order signals representative of nonlinear basis functions based on a joint time frequency representation of plural samples of the digital input signal;

weighting the plurality of higher order signals with predistortion coefficients to provide a predistortion correction signal; and

combining the predistortion correction signal with the digital input signal to provide a predistorted digital signal.

49. A method for digitally predistorting a digital input signal as set out in claim 48, wherein said nonlinear basis functions comprise truncated Gaussian functions based on a Gabor expansion of the input signal.

50. A method for adaptive digital predistortion linearization of an amplifier system, comprising:

receiving a digital input signal;

deriving a plurality of band limited higher order signals from the digital input signal;

weighting the plurality of band limited higher order signals with spectrally weighted predistortion coefficients to provide a predistortion correction signal;

combining the predistortion correction signal with the digital input signal to provide a predistorted digital signal;

converting the predistorted digital signal from digital to analog form to provide a predistorted analog signal;

up converting the predistorted analog signal to an RF signal;

amplifying the RF signal to provide an amplified RF output signal;

sampling the RF output signal;

down converting the sampled RF output signal to a lower frequency sampled analog output signal;

converting the lower frequency sampled analog output signal to digital form to provide a sampled digital output signal;

deriving an error signal from the input digital signal and the sampled digital output signal;

deriving spectrally weighted subsignals from the error signal and the digital input signal; and

adaptively generating said spectrally weighted predistortion coefficients from the spectrally weighted subsignals.