Semiconductor storage device, method for protecting predetermined memory element and portable electronic equipment

• US 20050002258A1
• Filed: 05/19/2004
• Published: 01/06/2005
• Est. Priority Date: 05/20/2003
• Status: Active Grant

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Iwata, Hiroshi, Shibata, Akihide, Yaoi, Yoshifumi, Iwase, Yasuaki, Morikawa, Yoshinao, Nawaki, Masaru
• Granted Patent: US 7,315,603 B2
• Time in Patent Office: Days
• US Class Current: 365/222
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: G11C 16/0458 comprising two or more independent floating gates which store independent data
• CPC Class Codes: G11C 16/0475 comprising two or more independent storage sites which store independent data
• CPC Class Codes: G11C 16/22 Safety or protection circuits preventing unauthorised or accidental access to memory cells
• CPC Class Codes: G11C 2216/06 Floating gate cells in which the floating gate consists of multiple isolated silicon islands, e.g. nanocrystals
• CPC Class Codes: G11C 7/24 Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells
• CPC Class Codes: H01L 29/40111 the electrodes comprising a layer which is used for its ferroelectric properties
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors

Abstract

There is provided a semiconductor storage device and portable electronic equipment including a nonvolatile memory element that can easily be miniaturized. The semiconductor storage device includes a memory cell array 21 in which a plurality of memory elements 1 are arranged and a write state machine 32. The memory element 1 includes a gate electrode 104 formed on a semiconductor layer 102 via a gate insulator 103, a channel region arranged below the gate electrode 104, diffusion regions 107a, 107b that are located on both sides of the channel region and have a conductive type opposite to that of the channel region and memory function bodies 109 that are located on both sides of the gate electrode 104 and have a function to retain electric charge. The write state machine 32 can selectively prevent program and erase of data in the memory elements within a predetermined range.

Claims

1. A semiconductor storage device comprising:

a memory cell array having a plurality of memory elements whose addresses can be designated;

a write state machine which is connected to the memory cell array, controls operations to be performed on the memory cell array, receives control signals that represent one operation or a sequence of operations to be performed at at least one block of at least one address in the memory cell array, receives predetermined bits of an identification of a block of addresses, further receives a protect signal, generates an active lock signal if the predetermined bit of the identification of the block of the addresses and the protect signal are in predetermined states, responds to the lock signal by failing to perform the operation identified, and responds to an absence of the lock signal by performing each operation identified on every address within the block; and

a command state machine which is connected so as to receive data including commands and generates control signals for controlling the write state machine and the protect signal,

each memory element of the memory cell array comprising;

a gate electrode formed on a semiconductor layer via a gate insulator;

a channel region disposed below the gate electrode via the gate insulator;

diffusion regions which are disposed on both sides of the channel region and have a conductive type opposite to a conductive type of the channel region; and

memory function bodies which are formed on both sides of the gate electrode and have a function to retain electric charge or polarization.

2. The semiconductor storage device as claimed in claim 1, wherein

the write state machine comprises:

an address counter which receives and buffers control signals to be applied to addresses within a given block of the memory cell array from the command state machine, and iteratively outputs signals to address memory elements in the memory cell array corresponding to the block of the addresses, and which further comprises a protected address detector which detects protected memory address and which senses a state of the protect signal by detecting a protected memory address, wherein the address counter outputs an active lock signal if the predetermined bits of an address are in predetermined states indicating that the address is to be protected and the protect signal is in a predetermined state indicating that the address is to be protected,

a state controller connected so as to receive the identification of the operation to be performed and the lock signal, wherein the state controller determines a state of the write state machine, and indicates that the state of the write state machine is a state in which the operation is not performed if the operation is an identified operation and the lock signal is active.

3. The semiconductor storage device as claimed in claim 2, wherein

the protected address detector comprises a multi-input AND gate connected so as to receive the predetermined bits of the address and the protect signal and outputs the lock signal.

4. The semiconductor storage device as claimed in claim 1, wherein:

the command state machine is connected so as to receive a command from a microprocessor and to receive the protect signal, the command state machine outputting control signals to the write state machine so as to perform the operation, and the command state machine further outputting the protect signal to the write state machine.

9. The semiconductor storage device as claimed in claim 1, wherein the memory element has an insulation film which insulates a film that has a surface roughly parallel to a surface of the gate insulator and a function to retain electric charge from the channel region or the semiconductor layer, and the insulation film has a film thickness thinner than a film thickness of the gate insulator and is not thinner than 0.8 nm.

11. Portable electronic equipment comprising the semiconductor storage device claimed in claim 1.

5. A semiconductor storage device comprising:

a memory cell array having a plurality of memory elements identified by addresses; and

a microprocessor for outputting commands of memory operations to be performed at at least one address in the memory cell array, wherein

the command outputted from the microprocessor includes an identification of at least one operation to be performed and an identification of at least one block of memory addresses, and wherein

the microprocessor further outputs a protect signal indicating that predetermined memory elements of the memory cell array are protected when the protect signal is in an active state,

the semiconductor storage device comprising a memory controller connected between the memory cell array and the microprocessor, wherein

the memory controller receives the commands, data and identifications of the blocks of the addresses and outputs operation control signals to perform the identified operation at the at least one address in the memory cell array, and wherein

the memory controller comprises a command state machine connected so as to receive the identification of at least one operation to be performed and the state of the protect signal, the command state machine outputting write state machine control signals comprising signals to identify the operation to be performed and a state of the protect signal, wherein

the memory controller further comprises a write state machine connected to the memory cell array to control operation to be performed on the memory cell array, the write state machine comprising a logic circuit connected so as to receive predetermined bits of the address and a write state machine control signal, the logic circuit generating an active lock signal if the predetermined bits of the address and the protect signal are in predetermined states, the write state machine responding to the active lock signal by failing to perform the operation identified, and

each memory element of the memory cell array comprising;

a gate electrode formed on a semiconductor layer via a gate insulator;

a channel region disposed below the gate electrode via the gate insulator;

diffusion regions which are disposed on both sides of the channel region and have a conductive type opposite to a conductive type of the channel region; and

memory function bodies which are formed on both sides of the gate electrode and have a function to retain electric charge or polarization.

6. The semiconductor storage device as claimed in claim 5, wherein

the write state machine comprises:

an address counter which receives and buffers the write state machine control signals to be applied to addresses in a given block of the memory cell array, and iteratively outputs control signals to address memory elements in the memory cell array corresponding to the block of the addresses, wherein

the address counter comprises a protected address detector which detects protected memory addresses and senses a state of the protect signal, the address counter outputting an active lock signal if the predetermined bits of the address are in predetermined states indicating that the address is to be protected and the protect signal is active,

the semiconductor storage device comprising a state controller connected so as to receive the identification of the operation to be performed and the lock signal, wherein

the state controller determines a state of the write state machine, and the state controller indicates that the state of the write state machine is a state in which the operation is not performed if the operation is an identified operation and the lock signal is active.

7. The semiconductor storage device as claimed in claim 6, wherein

the protected address detector comprises a multi-input AND gate connected to receive the predetermined bits of the address and the protect signal, and outputs the lock signal.

10. The semiconductor storage device as claimed in claim 5, wherein the memory element has an insulation film which insulates a film that has a surface roughly parallel to a surface of the gate insulator and a function to retain electric charge from the channel region or the semiconductor layer, and the insulation film has a film thickness thinner than a film thickness of the gate insulator and is not thinner than 0.8 nm.

12. Portable electronic equipment comprising the semiconductor storage device claimed in claim 5.

8. A method for protecting predetermined memory elements in a semiconductor storage device including a memory cell array having a plurality of memory elements identified by addresses, a microprocessor that outputs commands of memory operation to be performed at at least one address in the memory cell array, and a memory controller connected between the memory cell array and the microprocessor, wherein the commands outputted from the microprocessor comprise an identification of an operation to be performed and a memory address, the memory controller receiving the command and outputting control signals to perform the identified operation at the at least one address in the memory cell array, each memory element of the memory cell array comprising a gate electrode formed on a semiconductor layer via a gate insulator, a channel region disposed below the gate electrode via the gate insulator, diffusion regions that are disposed on both sides of the channel region and have a conductive type opposite to a conductive type of the channel region, and memory function bodies that are formed on both sides of the gate electrode and have a function to retain electric charge or polarization, the method comprising the steps of:

outputting a protect signal indicating that predetermined memory elements of the memory cell array are protected when the protect signal is in an active state from the microprocessor to the memory controller;

receiving predetermined bits of the address and the protect signal by the memory controller and generating a lock signal if the predetermined bits of the address and the protect signal are in predetermined states;

putting the memory controller into a state determined by a status of the protect signal and by an immediately preceding state of the memory controller, and making the memory controller operate on subsequent memory addresses determined by the state, such that the memory controller fails to perform the operation identified if the lock signal is generated, and performs the operation identified according to the state of the memory controller on addresses at which the operations identified are to be performed if the lock signal is not generated.