All-around MOSFET gate and methods of manufacture thereof

• US 20050003592A1
• Filed: 06/18/2003
• Published: 01/06/2005
• Est. Priority Date: 06/18/2003
• Status: Abandoned Application

• Current Assignee: Mindspeed Technologies Inc. (MACOM Technology Solutions Holdings, Inc.)
• Original Assignee: Mindspeed Technologies Inc. (MACOM Technology Solutions Holdings, Inc.)
• Inventors: Jones, A. Brooke
• Application Number:
  US10/465,087
• Publication Number:
  US 20050003592A1
• Time in Patent Office: Days
• US Class Current: 438/157
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

Metal oxide field effect transistor having a channel and a gate that surrounds the channel on four sides. Method of manufacture of the transistor includes processing the back of a silicon wafer to form a buried gate that is electrically connected to the gate of a conventional field effect transistor to form an all-around structure.

Claims

1-9. -9. (Cancelled).

10. A semiconductor element produced by a manufacturing method, said manufacturing method comprising:

oxidizing a wafer having a first surface so as to form an oxide on the first surface;

creating a void in the oxide to form a gate region;

partially filling the void with gate dielectric;

filling the remaining portion of the void with gate material;

bonding the first surface of the wafer to a substrate;

removing material from a surface of the wafer opposite the first surface to expose the separation plane;

processing the separation plane surface to create a field effect transistor having a gate; and

electrically connecting the gate of the field effect transistor to the gate material contained in the void.

11. The semiconductor element produced by the manufacturing method of claim 10 wherein bonding the first surface of the wafer to a substrate comprise:

blanketing the first surface with a dielectric layer; and

adhering the dielectric layer to a substrate.

12. The semiconductor element produced by the manufacturing method of claim 10 wherein separating the first surface comprises:

implanting the first surface of the wafer with hydrogen; and

cleaving the wafer at the hydrogen implantation boundary.

13. The semiconductor element produced by the manufacturing method of claim 10 wherein separating the first surface comprises grinding the wafer from the surface opposite the first surface.

14. The semiconductor element produced by the manufacturing method of claim 10 wherein partially filling the void with gate dielectric comprises growing a dielectric material in the void.

15. The semiconductor element produced by the manufacturing method of claim 10 wherein partially filling the void with gate dielectric comprises depositing a dielectric material in the void.

16. The semiconductor element produced by the manufacturing method of claim 10 wherein filling the remaining portion of the void with gate material comprises:

depositing a layer of gate material over the first surface; and

removing excess gate material surrounding the void.

17. The semiconductor element produced by the manufacturing method of claim 10 wherein electrically connecting the gate of the field effect transistor to the gate material contained in the void comprises:

providing an etch orifice in the gate material of the field effect transistor;

prolonging the duration of a contact etch process so as to remove dielectric sustantially under the etch orifice; and

depositing contact metal into the etch orifice so as to connect the gate material of the field effect transistor to the gate material contained in the void

18. The semiconductor element produced by the manufacturing method of claim 10 wherein electrically connecting the gate of the field effect transistor to the gate material contained in the void comprises:

exposing the gate material contained in the void to the separation plane surface; and

depositing gate material for the field effect transistor onto the gate material contained in the void.

19. An all-around gate metal oxide semiconductor field effect transistor comprising:

substrate comprising insulating material;

buried gate region that overlays the substrate, said buried gate region comprising;

layer of buried gate material, the bottom surface of which contacts the substrate, and

layer of gate dielectric material that overlays the buried gate material,

channel comprising silicon layer that overlays the gate dielectric material, said channel further comprising doped source and drain regions;

oxidized silicon that surrounds the buried gate region and the channel;

gate that overlays the channel so as to surround the channel on at least three sides, said gate comprising conducting material electrically isolated from the channel by gate dielectric material; and

one or more connections that electrically connect the gate to the layer of buried gate material in the buried gate region.

20. An all-around gate metal oxide semiconductor field effect transistor comprising:

substrate comprising conducting material;

dielectric layer that overlays the substrate buried gate region that overlays the substrate, said buried gate region comprising;

layer of buried gate material, the bottom surface of which contacts the substrate, and

layer of gate dielectric material that overlays the buried gate material,

channel comprising silicon layer that overlays the gate dielectric material, said channel further comprising doped source and drain regions;

oxidized silicon that surrounds the buried gate region and the channel;

gate that overlays the channel so as to surround the channel on at least three sides, said gate comprising conducting material electrically isolated from the channel by gate dielectric material; and

one or more connections that electrically connect the gate to the layer of buried gate material in the buried gate region.