Capacitor layout technique for reduction of fixed pattern noise in a CMOS sensor

• US 20050003624A1
• Filed: 07/01/2004
• Published: 01/06/2005
• Est. Priority Date: 08/13/2002
• Status: Active Grant

• Current Assignee: Giuseppe Rossi
• Original Assignee: Giuseppe Rossi
• Inventors: Rossi, Giuseppe
• Granted Patent: US 7,124,384 B2
• Time in Patent Office: Days
• US Class Current: 438/381
• CPC Class Codes: H01L 27/0805 Capacitors only
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H01L 29/94 Metal-insulator-semiconductors, e.g. MOS
• CPC Class Codes: Y10S 438/957 Making metal-insulator-metal device

Abstract

A new capacitor architecture includes a front plate of the capacitor formed form a first polysilicon layer. The front plate is surround by first and second dielectric layers. The back plate of the capacitor is formed from one layer of a first two-layer conductive structure which surrounds the first and second dielectric layer. The two layer structure is an equal potential structure and includes a conductive coupling between the two layers. In one embodiment, the back plate of the capacitor is formed from a metal layer. A third and fourth dielectric layers surround the first two-layer conductive structure. A second two-layer equal potential conductive structure surrounds the third and fourth dielectric layers. In one embodiment, the second two-layer equal potential conductive structure comprise an interconnect between a metal layer and the substrate.

Claims

1-72. -72. (canceled)

73. A capacitor, comprising:

a first plate;

a second plate;

a first shield, said first shield comprising a first surface and a second surface, said first and second surfaces being equal potential surfaces;

a second shield, said second shield comprising a third surface and a fourth surface, said third and fourth surfaces being equal potential surfaces;

wherein

said first and second plates are disposed to form two plates of said capacitor,

said first and second plates are disposed to shield said first plate,

and said third and fourth plates are disposed to shield said first and second plates. f

74. The capacitor of claim 73, wherein said second shield is disposed to also shield said first shield.

75. The capacitor of claim 73, wherein said capacitor is formed over a substrate.

76. The capacitor of claim 75, wherein one of said first and second surfaces is a polysilicon layer formed over said substrate.

77. The capacitor of claim 75, wherein one of said first and second surfaces is a metal layer formed over said substrate.

78. The capacitor of claim 75, wherein one of said third and four surfaces is said substrate formed over said substrate.

79. The capacitor of claim 75, wherein one of said third and four surfaces is a metal layer formed over said substrate.

80. The capacitor of claim 75, wherein one of said first and second plates is a metal layer formed over said substrate.

81. The capacitor of claim 75, wherein one of said first and second plates is a polysilicon layer formed over said substrate.

82. A circuit for sampling signals produced by a pixel, comprising:

an input line for receiving signals produced by said pixel;

a sample capacitor; and

a switch for controllably coupling said sample capacitor to said input line;

wherein said sample capacitor is fabricated as a semiconductor device and further comprises;

a first plate;

a second plate;

a first shield, said first shield comprising a first surface and a second surface, said first and second surfaces being equal potential surfaces;

a second shield, said second shield comprising a third surface and a fourth surface, said third and fourth surfaces being equal potential surfaces;

wherein

said first and second plates are disposed to form two plates of said capacitor,

said first and second plates are disposed to shield said first plate,

and said third and fourth plates are disposed to shield said first and second plates.

83. The circuit of claim 82, wherein said second shield is disposed to also shield said first shield.

84. The circuit of claim 82, wherein said capacitor is formed over a substrate.

85. The circuit of claim 84, wherein one of said first and second surfaces is a polysilicon layer formed over said substrate.

86. The circuit of claim 84, wherein one of said first and second surfaces is a metal layer formed over said substrate.

87. The circuit of claim 84, wherein one of said third and four surfaces is said substrate formed over said substrate.

88. The circuit of claim 84, wherein one of said third and four surfaces is a metal layer formed over said substrate.

89. The circuit of claim 84, wherein one of said first and second plates is a metal layer formed over said substrate.

90. The circuit of claim 84, wherein one of said first and second plates is a polysilicon layer formed over said substrate.