Use of ammonia for etching organic low-k dielectrics

• US 20050003676A1
• Filed: 01/21/2004
• Published: 01/06/2005
• Est. Priority Date: 02/12/2001
• Status: Active Grant

• Current Assignee: Chok W. Ho, Chung-Ju Lee, Kuo-Lung Tang
• Original Assignee: Chok W. Ho, Chung-Ju Lee, Kuo-Lung Tang
• Inventors: Lee, Chung-Ju, Tang, Kuo-Lung, Ho, Chok W.
• Granted Patent: US 7,105,454 B2
• Time in Patent Office: Days
• US Class Current: 438/725
• CPC Class Codes: H01L 21/31138 by dry-etching
• CPC Class Codes: H01L 21/31144 using masks

Abstract

Method for etching organic low-k dielectric using ammonia, NH3, as an active etchant. Processes using ammonia results in at least double the etch rate of organic low-k dielectric materials than processes using N2/H2 chemistries, at similar process conditions. The difference is due to the much lower ionization potential of NH3 versus N2 in the process chemistry, which results in significantly higher plasma densities and etchant concentrations at similar process conditions.

Claims

1-16. -16. (Cancelled).

17. An integrated circuit formed from an etched organic low-k dielectric layer over a substrate, made from the steps comprising:

placing a hard mask over the organic low-k dielectric layer;

placing a patterned photoresist layer over the hard mask layer;

placing the substrate in an etching chamber;

providing an etchant gas comprising NH3 into the etching chamber;

generating a plasma from the NH3, which etches the organic dielectric layer, which is able to selectively etch the organic low-k dielectric layer with respect to the hard mask and strip the photoresist layer;

selectively etching the organic low-k dielectric layer with respect to the hard mask; and

simultaneously stripping the photo resist layer during the selective etching of the organic low-k dielectric layer.

18. The integrated circuit, as recited in claim 17, wherein the NH3 has a flow rate between 100 sccm to 1000 sccm.

20. The integrated circuit, as recited in claim 17, wherein the NH3 has a flow rate from about 300 sccm to about 800 sccm.

21. The integrated circuit, as recited in claim 20, further comprising maintaining the substrate at a temperature between about 10°

C. to about 40°

C. during etching of the organic dielectric layer.

22. The integrated circuit, as recited in claim 17, further comprising providing a bias power of between about 0 W and 100 W during etching of the organic low-k dielectric layer.

23. The integrated circuit, as recited in claim 17, further comprising:

placing an etch stop layer over the organic low-k dielectric layer;

placing a second organic low-k dielectric layer over the etch stop layer, wherein the second organic low-k dielectric layer is between the organic low-k dielectric layer and the hardmask.

24. The integrated circuit, as recited in claim 23, further comprising etching the second organic low-k dielectric layer with a first etch, wherein the first etch provides a bias power of between about 250 W to about 2500 W before selectively etching the organic low-k dielectric layer.

25. The integrated circuit, as recited in claim 24, further comprising providing a bias power of between about 0 W and 100 W during etching of the organic dielectric layer.

26. The integrated circuit, as recited in claim 25, further comprising providing an etchant gas comprising CF4 for the etching the second low-k organic dielectric layer.

27. The integrated circuit, as recited in claim 26, wherein the etchant gas comprising CF4 further comprises C4F8.

28. The integrated circuit, as recited in claim 27, wherein the etchant gas comprising NH3 uses NH3 alone as the etchant.

29. The integrated circuit, as recited in claim 17, wherein the simultaneous stripping completely strips the photoresist.

30. The integrated circuit, as recited in claim 17, wherein the etchant gas comprising NH3 uses NH3 alone as the etchant.

19. (Canceled).

31. An integrated circuit formed by a method of etching an organic dielectric layer over a substrate, comprising:

placing a hard mask over the organic dielectric layer;

placing a patterned photoresist layer over the hard mask layer;

placing the substrate in an etching chamber;

providing an etchant gas comprising NH3 into the etching chamber, wherein the NH3 has a flow rate between 5 sccm to 1500 sccm;

generating a plasma from the NH3, which selectively etches the organic dielectric layer with respect to the hardmask; and

simultaneously stripping the photo resist layer during the etching of the organic dielectric layer.

32. The integrated circuit, as recited in claim 31, further comprising providing CH3F while providing the etchant gas comprising NH3.

33. The integrated circuit, as recited in claim 32, further comprising providing an etch with an etchant gas comprising CF4, prior to the step of providing the etchant gas comprising NH3.

34. The integrated circuit, as recited in claim 33, wherein the etchant gas comprising CF4, further comprises C4F8.

35. The integrated circuit, as recited in claim 34, wherein the etchant gas comprising CF4 further comprises O2.

36. The integrated circuit, as recited in claim 31, wherein the organic dielectric layer is made of an organic low-k material, and wherein the simultaneous stripping completely strips the photoresist layer.

37. An integrated circuit formed by a method of etching an organic dielectric layer disposed below a hardmask layer and over a substrate, comprising:

placing the substrate in an etching chamber;

providing an etchant gas comprising NH3 into the etching chamber with a flow rate from about 300 sccm to about 800 sccm;

generating a plasma from the NH3, which etches the organic dielectric layer; and

maintaining the substrate at a temperature between about 10°

C. to about 40°

C. during the etching of the organic dielectric layer.