Methods and systems for inspection of wafers and reticles using designer intent data

• US 20050004774A1
• Filed: 07/01/2004
• Published: 01/06/2005
• Est. Priority Date: 07/03/2003
• Status: Active Grant

• Current Assignee: Kla-Tencor Technologies Corporation (KLA Corporation)
• Original Assignee: Kla-Tencor Technologies Corporation (KLA Corporation)
• Inventors: Chang, Ellis, Wiley, James, Marella, Paul Frank, Kekare, Sagar A., Hess, Carl, McCauley, Sharon, Watson, Sterling, Volk, William
• Granted Patent: US 9,002,497 B2
• Time in Patent Office: Days
• US Class Current: 702/108
• CPC Class Codes: G01N 2021/95676 Masks, reticles, shadow masks
• CPC Class Codes: G01N 21/9501 Semiconductor wafers manufacturing processes per se of semiconductor devices implementing a measuring step H01L22/10
• CPC Class Codes: G01N 21/956 Inspecting patterns on the surface of objects contactless testing of electronic circuits G01R31/308; testing currency G07D; manufacturing processes per se of semiconductor devices implementing a measuring step H01L22/10
• CPC Class Codes: G03F 1/84 Inspecting
• CPC Class Codes: G03F 7/7065 Defects, e.g. optical inspection of patterned layer for defects
• CPC Class Codes: G06T 2207/30148 Semiconductor; IC; Wafer
• CPC Class Codes: G06T 7/0006 using a design-rule based approach
• CPC Class Codes: G06T 7/0008 checking presence/absence

Abstract

Methods and systems for inspection of wafers and reticles using designer intent data are provided. One computer-implemented method includes identifying nuisance defects on a wafer based on inspection data produced by inspection of a reticle, which is used to form a pattern on the wafer prior to inspection of the wafer. Another computer-implemented method includes detecting defects on a wafer by analyzing data generated by inspection of the wafer in combination with data representative of a reticle, which includes designations identifying different types of portions of the reticle. An additional computer-implemented method includes determining a property of a manufacturing process used to process a wafer based on defects that alter a characteristic of a device formed on the wafer. Further computer-implemented methods include altering or simulating one or more characteristics of a design of an integrated circuit based on data generated by inspection of a wafer.

Claims

1. A computer-implemented method, comprising identifying nuisance defects on a wafer based on inspection data produced by inspection of a reticle, wherein the reticle is used to form a pattern on the wafer prior to inspection of the wafer.

2. The method of claim 1, wherein the nuisance defects are formed on the wafer as a result of defects on the reticle that were determined to be permissible reticle defects.

3. The method of claim 1, wherein the nuisance defects are formed on the wafer as a result of defects on the reticle that were determined to be permissible reticle defects based on designer intent data.

4. The method of claim 1, further comprising separating the nuisance defects from actual defects on the wafer and processing data representative of the actual defects.

5. The method of claim 1, further comprising transmitting the inspection data from an inspection system used to perform the inspection of the reticle to a processor configured to perform the method.

6. The method of claim 1, further comprising transmitting the inspection data from a fab database to a processor configured to perform the method.

7. The method of claim 6, wherein said transmitting comprises sending coordinates of defects detected on the reticle and images of the defects.

8. The method of claim 1, wherein the inspection data comprises coordinates of a location of a defect on the reticle, the method further comprising translating the coordinates to coordinates of locations of one or more of the nuisance defects on the wafer.

9. The method of claim 1, further comprising determining if the nuisance defects will affect yield of semiconductor devices, wherein the semiconductor devices will be formed on the wafer.

10. The method of claim 1, wherein the nuisance defects are formed on the wafer as a result of defects on the reticle that were determined to be permissible reticle defects, the method further comprising analyzing the nuisance defects to determine if the permissible reticle defects were correctly classified.

11. The method of claim 10, wherein if the permissible reticle defects were not correctly classified, the method further comprising determining if the reticle should be analyzed, reworked, or disposed.

12. The method of claim 1, further comprising generating a two-dimensional map of the wafer, wherein the nuisance defects are distinguished from other defects in the map by one or more different designations.

13. A computer-implemented method, comprising identifying locations on a wafer in which nuisance defects will be formed based on inspection data produced by inspection of a reticle.

14. The method of claim 13, further comprising selecting one or more parameters for wafer inspection such that the locations are not inspected.

15. The method of claim 13, further comprising selecting one or more parameters for wafer defect review such that the nuisance defects are not reviewed.

16. The method of claim 13, further comprising selecting one or more parameters for wafer defect analysis such that the nuisance defects are not analyzed.

17. A computer-implemented method, comprising:

identifying critical portions of a wafer based on criticality associated with different areas of the wafer; and

selecting parameters for inspection of the wafer such that only the critical portions of the wafer are inspected.

18. The method of claim 17, wherein the parameters are selected such that the critical portions having different criticalities are inspected with different parameters.

19. The method of claim 17, further comprising translating coordinates of a location of a defect detected on a reticle to coordinates of locations of one or more defects on the wafer and analyzing the printability of the defect detected on the reticle.

20. The method of claim 17, further comprising translating coordinates of a location of a defect detected on a reticle to coordinates of locations of one or more defects on the wafer and removing inspection data at the coordinates on the wafer from wafer inspection data.

21. The method of claim 17, further comprising generating one or more two-dimensional maps illustrating the critical portions of the wafer.

22. The method of claim 17, wherein said selecting comprises selecting the parameters such that nuisance defects on the wafer are not classified as actual defects.

23. The method of claim 17, further comprising assigning a designation to a defect on the wafer based on the criticality of the critical portion in which the defect is located.

24. The method of claim 17, further comprising determining processing of a defect on the wafer based on the criticality of the critical portion in which the defect is located.

25. The method of claim 17, further comprising setting one or more parameters for classification of defects on the wafer based on the criticality of the critical portions.

26. The method of claim 17, further comprising classifying defects on the wafer as critical defects or non-critical defects and analyzing a process performed on the wafer based on the critical defects and the non-critical defects.

27. The method of claim 17, further comprising classifying defects on the wafer as critical defects or non-critical defects and processing the critical defects separately from the non-critical defects.

28. The method of claim 17, further comprising discarding inspection data representing defects in one of the critical portions if the defects have a lateral dimension smaller than a predetermined threshold and if other features in the one portion have a lateral dimension greater than the predetermined threshold.

29. The method of claim 17, further comprising discarding inspection data representing defects in one of the critical portions if an element of a circuit in the one portion has a predetermined amount of redundancy and if defects in the one portion do not exceed a predetermined density threshold.

30. The method of claim 17, wherein the inspection is performed on one level of the wafer, the method further comprising identifying the criticality of a defect on the wafer based on the criticality of the critical portion in which the defect is located and data representative of at least one layer of the wafer above or below the one level.

31. The method of claim 30, further comprising generating a three-dimensional representation of the defect, the one level, and the at least one layer of the wafer.

32. A computer-implemented method, comprising determining one or more parameters for wafer defect review based on criticality associated with different areas of the wafer.

33. The method of claim 32, further comprising selecting the one or more parameters such that only defects located in critical portions of the wafer are reviewed.

34. The method of claim 33, wherein the one or more parameters are different for one or more of the critical portions.

35. The method of claim 32, further comprising sending information about the criticality to a tool configured to perform the wafer defect review.

36. A computer-implemented method, comprising determining one or more parameters for wafer defect analysis based on criticality associated with different areas of the wafer.

37. The method of claim 36, further comprising selecting the one or more parameters such that only defects located in critical portions of the wafer are analyzed.

38. The method of claim 37, wherein the one or more parameters are different for one or more of the critical portions.

39. The method of claim 36, further comprising sending information about the criticality to a tool configured to perform the wafer defect analysis.

40. A computer-implemented method, comprising:

identifying bad die on a wafer, wherein the bad die contain one or more electrical elements having functionality outside of a predetermined range;

identifying a first portion of defects and a second portion of defects on the wafer based on data generated by inspection of the wafer in combination with information representative of a design of the one or more electrical elements, wherein the first portion of the defects alters a characteristic of a device formed by the one or more electrical elements such that the characteristic is outside of predetermined limits; and

determining a property of a manufacturing process used to process the wafer based on the first portion of the defects.

41. The method of claim 40, wherein the property comprises a kill ratio of the first portion of the defects.

42. The method of claim 40, wherein the property comprises a yield of the manufacturing process.

43. The method of claim 40, wherein the data comprises data generated by multiple inspections of the wafer, and wherein the multiple inspections are performed at different times during the manufacturing process.

44. The method of claim 40, wherein said identifying the bad die comprises performing functional testing on the wafer after the manufacturing process is completed.

45. The method of claim 40, further comprising altering one or more parameters of the manufacturing process based on the property.

46. A computer-implemented method, comprising altering a design of an integrated circuit based on data generated by inspection of a wafer during a manufacturing process, wherein the data comprises information about defects detected on the wafer, and wherein a substantial portion of the defects comprises critical defects that can alter one or more characteristics of the integrated circuit.

47. The method of claim 46, wherein said altering is performed using a feedback control technique.

48. The method of claim 46, wherein said altering comprises altering the design of the integrated circuit to reduce a number of the critical defects that are formed during the manufacturing process.

49. The method of claim 46, further comprising distinguishing between the critical defects and other non-critical defects detected during the inspection based on the design, wherein the non-critical defects will not substantially alter the one or more characteristics of the integrated circuit.

50. The method of claim 46, further comprising identifying individual processes of the manufacturing process that result in at least some of the critical defects being formed on the wafer.

51. The method of claim 50, further comprising determining if the design of the integrated circuit contributes to formation of the critical defects.

52. The method of claim 51, wherein said altering comprises altering the design of the integrated circuit to reduce a number of the critical defects that are formed during the individual processes.

53. The method of claim 46, further comprising determining a yield of the manufacturing process based on the critical defects, wherein said altering comprising altering the design of the integrated circuit to increase the yield of the manufacturing process.

54. The method of claim 46, further comprising altering the manufacturing process based on the data.

55. A storage medium, comprising:

data representative of an integrated circuit design;

data representative of an integrated circuit manufacturing process; and

defect data representative of defects detected on a wafer during the integrated circuit manufacturing process, wherein the defect data is filtered such that a substantial portion of the defects comprises critical defects that can alter one or more characteristics of the integrated circuit, and wherein the storage medium can be used to alter the integrated circuit design based on the data representative of the integrated circuit design, the data representative of the integrated circuit manufacturing process, and the defect data.

56. The storage medium of claim 55, further comprising data representative of relationships between the critical defects and the integrated circuit design.

57. A computer-implemented method, comprising simulating one or more characteristics of an integrated circuit based on data generated by inspection of a wafer during a manufacturing process, wherein the data comprises information about defects detected on the wafer, and wherein a substantial portion of the defects comprises critical defects that can alter the one or more characteristics of the integrated circuit.

58. The method of claim 57, further comprising distinguishing between the critical defects and non-critical defects detected during the inspection based on design information, wherein the non-critical defects will not substantially alter the one or more characteristics of the integrated circuit.

59. The method of claim 57, wherein the information about the defects comprises coordinates of defect locations and three-dimensional defect profiles.

60. The method of claim 57, wherein the one or more characteristics comprises voltage drops, timing slowdowns, partial device failure, and total device failure.

61. A computer-implemented method, comprising determining placement of a pattern on a specimen based on data generated by inspection of the specimen.

62. The method of claim 61, wherein the specimen comprises a blank reticle substrate.

63. The method of claim 61, wherein the specimen comprises a wafer.

64. The method of claim 61, wherein said determining comprises selecting the placement of the pattern such that a substantial portion of defects on the specimen does not overlap with the pattern.

65. The method of claim 61, further comprising identifying critical portions of the pattern based on design information, wherein said determining comprises determining the placement of the critical portions of the pattern with respect to locations of defects on the specimen.

66. The method of claim 61, wherein said determining comprises selecting the placement of the pattern such that a substantial portion of defects on the specimen does not overlap with critical portions of the pattern.

67. The method of claim 61, wherein said determining comprises selecting the placement of the pattern such that an amount of overlap between defects on the specimen and critical portions of the pattern is below a predetermined threshold.

68. The method of claim 61, wherein the specimen comprises a reticle, the method further comprising determining an amount of overlap between defects on the reticle and critical portions of the pattern and estimating a number of critical defects that would be produced on a wafer that is exposed with the reticle.

69. The method of claim 61, wherein said determining comprises laterally translating the pattern, rotating the pattern, scaling the pattern, or any combination thereof.

70. The method of claim 61, wherein the specimen comprises a reticle, the method further comprising determining aligmment of the reticle with an exposure tool or a wafer based on the placement of the pattern with respect to a coordinate system.

71. A computer-implemented method, comprising:

determining a design significance of a defect detected on a reticle, wherein the design significance is a measure of how the defect impacts a design of the reticle;

determining a lithographic significance of the defect, wherein the lithographic significance is a measure of how the defect impacts a wafer patterned by a lithography process that uses the reticle; and

determining an overall significance of the defect based on the design significance and the lithographic significance.

72. The method of claim 71, further comprising determining a design significance of different regions on the reticle, wherein said determining the design significance of the defect is based on the design significance of the region on the reticle in which the defect is located.

73. The method of claim 71, wherein said determining the design significance comprises comparing data representative of the defect to a threshold and determining that the defect has design significance if the data is greater than the threshold.

74. The method of claim 71, wherein said determining the design significance comprises comparing data representative of the defect to a threshold, and wherein the threshold varies depending on a location of the defect on the reticle.

75. The method of claim 71, further comprising determining a lithographic significance of different regions on the reticle, wherein said determining the lithographic significance of the defect is based on the lithographic significance of the region on the reticle in which the defect is located.

76. The method of claim 71, wherein said determining the lithographic significance comprises comparing data representative of the defect to a threshold and determining that the defect has lithographic significance if the data is greater than the threshold.

77. The method of claim 71, wherein said determining the lithographic significance comprises comparing data representative of the defect to a threshold, and wherein the threshold varies depending on a location of the defect on the reticle.

78. The method of claim 71, wherein the overall significance is selected from the group consisting of lithographically and design significant, lithographically significant only, design significant only, and not significant.

79. The method of claim 71, further comprising determining an overall significance of different regions on the reticle and determining one or more parameters of a process used to fabricate the different regions of the reticle based on the overall significance of the different regions such that the one or more parameters of the process in one of the different regions is different than the one or more parameters of the process in another of the different regions.

80. The method of claim 71, further comprising determining an overall significance of different regions on the reticle and altering one or more parameters of a process used to inspect the different regions of the reticle based on the overall significance of the different regions such that the one or more parameters of the process in one of the different regions is different than the one or more parameters of the process in another of the different regions.

81. The method of claim 71, further comprising determining an overall significance of different regions on the reticle and altering one or parameters of a process used to repair the reticle based on the overall significance of the different regions such that the one or more parameters of the process in one of the different regions is different than the one or more parameters of the process in another of the different regions.

82. The method of claim 71, further comprising determining one or more parameters of a process used to repair the defect based on the overall significance of the defect, wherein the one or more parameters used to repair different defects on the reticle are different.

83. The method of claim 71, further comprising determining processing of the reticle based on the overall significance of the defect, wherein the processing comprises rejecting the reticle, repairing the reticle, or cleaning the reticle.

84. The method of claim 71, further comprising generating a visual representation of the defect, wherein the visual representation comprises one or more designations assigned to the defect indicating the overall significance of the defect.

85. The method of claim 71, further comprising generating a visual representation of a plurality of individual regions on the reticle, wherein the visual representation comprises designations assigned to the individual regions indicating the overall significance of the individual regions.