System and method for expanding processor functionality

• US 20050005067A1
• Filed: 04/16/2003
• Published: 01/06/2005
• Est. Priority Date: 04/16/2003
• Status: Active Grant

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Morrison, John A., Nicholes, Martin O., Culter, Bradley G.
• Granted Patent: US 7,146,488 B2
• Time in Patent Office: Days
• US Class Current: 711/118
• CPC Class Codes: G06F 9/4403 Processor initialisation
• CPC Class Codes: G06F 9/4486 Formation of subprogram jump address

Abstract

A system comprises at least one processor, and supporting firmware for supporting at least one function of the at least one processor. The system further comprises logic operable to expand the functionality of the at least one function in a fashion that is not natively supported by the supporting firmware, and an interposer for supporting the expanded functionality of the at least one function. A method for expanding the functionality of an execution unit of a system comprises implementing an execution unit in a system, and implementing pre-existing support firmware for the execution unit in the system, wherein the pre-existing support firmware supports at least one function of the execution unit. The method further comprises implementing logic expanding the at least one function in a manner not supported by the pre-existing support firmware, and implementing an interposer to support the expansion of the at least one function.

Claims

1. A system comprising:

at least one processor;

supporting firmware for supporting at least one function of said at least one processor;

logic operable to expand the functionality of said at least one function in a fashion that is not natively supported by said supporting firmware; and

an interposer for supporting the expanded functionality of said at least one function.

2. The system of claim 1 wherein said at least one processor comprises an Intel Architecture (IA)-64 processor.

3. The system of claim 2 wherein said supporting firmware comprises Processor Abstraction Layer (PAL) firmware.

4. The system of claim 1 wherein said at least one function of said at least one processor comprises access to said at least one processor'"'"'s cache.

5. The system of claim 4 wherein said logic operable to expand the functionality of said at least one function comprises logic providing access to an expanded cache for said at least one processor.

6. The system of claim 1 wherein said interposer comprises an interface that is transparent to said supporting firmware.

7. The system of claim 1 further comprising:

an initiator for initiating the expanded functionality.

8. The system of claim 7 wherein said initiator comprises an operating system.

9. The system of claim 7 wherein said interposer comprises an interface that is transparent to said initiator.

10. The system of claim 7 wherein said interposer intercepts a call from said initiator intended for said supporting firmware.

11. The system of claim 10 wherein said call comprises a call to flush a cache of said at least one processor.

12. A method for expanding the functionality of an execution unit of a system, said method comprising:

implementing an execution unit in a system;

implementing pre-existing support firmware for said execution unit in said system, wherein said pre-existing support firmware supports at least one function of said execution unit;

implementing logic expanding said at least one function in a manner not supported by said pre-existing support firmware; and

implementing an interposer to support the expansion of said at least one function.

13. The method of claim 12 further comprising:

implementing said interposer to intercept calls from an initiator intended for said pre-existing support firmware.

14. The method of claim 13 further comprising:

providing said initiator an address for said interposer to be used by said initiator in accessing said pre-existing support firmware.

15. The method of claim 13 wherein said initiator comprises an operating system.

16. The method of claim 12 wherein said at least one function supported by said pre-existing support firmware comprises access to a first cache, and wherein the expansion of said at least one function comprises access to an additional cache.

17. The method of claim 12 wherein said execution unit comprises a processor.

18. A method for supporting an expanded function of an execution unit of a system, said method comprising:

intercepting a call intended for support firmware of an execution unit of a system;

determining whether said call is for an expanded function of said execution unit that is not supported by said support firmware; and

if said call is for said expanded function, using logic other than said support firmware to support said call for said expanded function.

19. The method of claim 18 further comprising:

using a combination of both said support firmware and said logic other than said support firmware to support said call.

20. The method of claim 18 wherein said expanded function comprises an expansion to a function that is supported by said support firmware, but wherein said support firmware does not support said expansion.

21. The method of claim 20 wherein said function that is supported by said support firmware comprises access to a first cache, and wherein said expanded function comprises access to an additional cache.

22. The method of claim 18 wherein said call comprises a call to flush a cache of said execution unit.

23. The method of claim 18 further comprising:

if said call is not for said expanded function of said execution unit, directing said call to said support firmware to support said call.

24. The method of claim 18 wherein said intercepting comprises:

intercepting said call from an initiator wherein said initiator is unaware of logic performing said intercepting.

25. The method of claim 24 wherein said initiator comprises an operating system.

26. The method of claim 18 wherein said execution unit comprises a processor.

27. A system comprising:

at least one execution unit;

first layer of supporting firmware for supporting said at least one execution unit; and

second layer of supporting firmware for supporting an enhancement to said at least one execution unit, wherein said enhancement is not supported by said first layer of supporting firmware and wherein said second layer of supporting firmware comprises an interface that is transparent to said first layer of supporting firmware.

28. The system of claim 27 wherein said at least one execution unit comprises an Intel Architecture (IA)-64 processor.

29. The system of claim 28 wherein said first layer of supporting firmware comprises Processor Abstraction Layer (PAL) firmware.

30. The system of claim 27 wherein said enhancement to said at least one execution unit comprises an additional cache for said at least one execution unit.

31. The system of claim 27 further comprising:

an initiator for accessing enhancement.

32. The system of claim 31 wherein said initiator comprises an operating system.

33. The system of claim 31 wherein said second layer of supporting firmware comprises an interface that is transparent to said initiator.

34. The system of claim 33 wherein said enhancement appears to said initiator to be supported by said first layer of supporting firmware.

35. The system of claim 31 wherein said second layer of supporting firmware is operable to intercept a call from said initiator intended for said first layer of supporting firmware.

36. A system comprising:

at least one processor;

Processor Abstraction Layer (PAL) firmware for supporting a function of said at least one processor;

logic expanding said function of said at least one processor in a fashion that is not natively supported by said PAL firmware; and

interposer firmware for supporting said expanded functionality.

37. The system of claim 36 wherein said at least one processor comprises an Intel Architecture (IA)-64 processor.

38. The system of claim 36 wherein said function of said at least one processor comprises access to said at least one processor'"'"'s cache.

39. The system of claim 38 wherein said logic expanding said function comprises logic adding a cache for said at least one processor.