Cryptographic-key management device

• US 20050005156A1
• Filed: 05/12/2004
• Published: 01/06/2005
• Est. Priority Date: 05/13/2003
• Status: Abandoned Application

• Current Assignee: BSI2000, Inc.
• Original Assignee: BSI2000, Inc.
• Inventors: Harper, W. Jack
• Application Number:
  US10/844,963
• Publication Number:
  US 20050005156A1
• Time in Patent Office: Days
• US Class Current: 726/26
• CPC Class Codes: H04L 2209/12 Details relating to cryptographic hardware or logic circuitry
• CPC Class Codes: H04L 2209/56 Financial cryptography, e.g. electronic payment or e-cash
• CPC Class Codes: H04L 2209/805 Lightweight hardware, e.g. radio-frequency identification [RFID] or sensor
• CPC Class Codes: H04L 9/0662 with particular pseudorandom sequence generator
• CPC Class Codes: H04L 9/0897 involving additional devices, e.g. trusted platform module [TPM], smartcard or USB
• CPC Class Codes: H04L 9/3247 involving digital signatures
• CPC Class Codes: H04L 9/3297 involving time stamps, e.g. generation of time stamps
• CPC Class Codes: H04L 9/50 using hash chains, e.g. blockchains or hash trees

Abstract

A cryptographic-key management device is provided. A secure cryptographic module is provided with a first memory storing a private cryptographic key of multiple public/private key pairs. The secure cryptographic module is adapted to zeroize the first memory in response to physical disruption of the module. A secure microcontroller is provided in communication with and adapted to control operation of the secure cryptographic module. The secure microcontroller has a second memory storing the public keys of the public/private key pains and a self-destruct pin whose activation disables the microcontroller. A package encapsulates the secure cryptographic module and the secure microcontroller, and is linked with the self-destruct pin to activate the self-destruct pin in response to a breach of the package.

Claims

1. A cryptographic-key management device comprising:

a secure cryptographic module comprising a first memory storing a private cryptographic key of a plurality of public/private key pairs, the secure cryptographic module adapted to zeroize the first memory in response to physical disruption of the module;

a secure microcontroller in communication with and adapted to control operation of the secure cryptographic module, the secure microcontroller comprising a second memory storing the public keys of the plurality of public/private key pairs and a self-destruct pin whose activation disables the microcontroller; and

a package encapsulating the secure cryptographic module and the secure microcontroller, the package linked with the self-destruct pin to activate the self-destruct pin in response to a breach of the package.

2. The cryptographic-key management device recited in claim 1 wherein the physical disruption of the module comprises a breach of a container housing the first memory.

3. The cryptographic-key management device recited in claim 1 wherein the physical disruption of the module comprises a deviation in a temperature of the module outside of a predefined range.

4. The cryptographic-key management device recited in claim 1 wherein the physical disruption of the module comprises a deviation in strength of an electromagnetic field near the module outside of a predefined range.

5. The cryptographic-key management device recited in claim 1 wherein the package comprises a brittle wire connected with the self-destruct pin.

6. The cryptographic-key management device recited in claim 5 wherein the brittle wire is wrapped about the secure cryptographic module and secure microcontroller.

7. The cryptographic-key management device recited in claim 6 wherein the brittle wire is wrapped in multiple layers about the secure cryptographic module and secure microcontroller.

8. The cryptographic-key management device recited in claim 1 wherein the package comprises an encapsulating material that includes an epoxy substance and at least one of a silica and an alumina.

9. The cryptographic-key management device recited in claim 1 wherein the secure microcontroller comprises a second self-destruct pin whose activation disables the microcontroller, the second self-destruct pin connected with a tamper sensor external to the cryptographic-key management device and internal to a housing surrounding the cryptographic-key management device.

10. The cryptographic-key management device recited in claim 1 further comprising a random-number generator in communication with the secure microcontroller.

11. The cryptographic-key management device recited in claim 10 wherein the random-number generator is a hardware random-number generator.

12. A method for fabricating a cryptographic-key management device, the method comprising:

providing a secure cryptographic module comprising a first memory and adapted to zeroize the first memory in response to physical disruption of the module;

providing a secure microcontroller in communication with the secure cryptographic module, the secure microcontroller comprising a second memory and a self-destruct pin whose activation disables the microcontroller;

storing a private cryptographic key of a plurality of public/private key pairs in the first memory;

storing the public keys of the plurality of public/private key pains in the second memory; and

encapsulating the secure cryptographic module and the secure microcontroller within a package linked with the self-destruct pin to activate the self-destruct pin in response to a breach of the package.

13. The method recited in claim 12 wherein the physical disruption of the module comprises a breach of a container housing the first memory.

14. The method recited in claim 12 wherein the physical disruption of the module comprises a deviation in a temperature of the module outside of a predefined range.

15. The method recited in claim 12 wherein the physical disruption of the module comprises a deviation in strength of an electromagnetic field near the module outside of a predefined range.

16. The method recited in claim 12 wherein encapsulating the secure cryptographic module and the secure microcontroller within a package comprises connecting a brittle wire with the self-destruct pin.

17. The method recited in claim 16 wherein encapsulating the secure cryptographic module and the secure microcontroller within a package further comprises wrapping the brittle wire about the secure cryptographic module and secure microcontroller.

18. The method recited in claim 17 wherein wrapping the brittle wire about the secure cryptographic module and secure microcontroller comprises wrapping the brittle wire in multiple layers about the secure cryptographic module and secure microcontroller.

19. The method recited in claim 12 wherein the package comprises an encapsulating material than includes an epoxy substance and at least one of a silica and an alumina.

20. The method recited in claim 12 wherein the secure microcontroller comprises a second self-destruct pin whose activation disables the microcontroller, the method further comprising connecting the second self-destruct pin with a tamper sensor.

21. The method recited in claim 12 further comprising providing a random number generator in communication with the secure microcontroller.

22. The method recited in claim 21 wherein the random number generator is a hardware random-number generator.

23. An optical-card network comprising:

a plurality of transaction processing units, each such unit comprising;

a cryptographic-key management device having a securely stored private key for that cryptographic-key management device and securely stored public keys for a plurality of cryptographic-key management devices comprised by the network;

an optical-card read/write drive in communication with the cryptographic-key management device and adapted to exchange data with optical cards; and

a processor in communication with and adapted to control operation of the cryptographic-key management device and the optical-card read/write drive; and

a plurality of optical cards.

24. The optical-card network recited in claim 23 wherein information may be exchanged among the plurality of transaction processing units only with the plurality of optical cards.

25. The optical-card network recited in claim 23 wherein the plurality of transaction processing units are interconnected electronically.

26. The optical-card network recited in claim 23 wherein the cryptographic-key management device comprises:

a secure cryptographic module comprising a first memory storing the private cryptographic key and adapted to zeroize the first memory in response to physical disruption of the module;

a secure microcontroller in communication with and adapted to control operation of the secure cryptographic module, the secure microcontroller comprising a second memory storing the public keys and a self-destruct pin whose activation disables the microcontroller; and

a package encapsulating the secure cryptographic module and the secure microcontroller, the package linked with the self-destruct pin to activate the self-destruct pin in response to a breach of the package.

27. The optical-card network recited in claim 26 wherein the package comprises a brittle wire connected with the self-destruct pin and wrapped about the secure cryptographic module and secure microcontroller.

28. The optical-card network recited in claim 26 wherein the package comprises an epoxy substance and at least one of a silica and an alumina.

29. The optical-card network recited in claim 26 wherein:

the each such unit further comprises a tamper sensor; and

the secure microcontroller comprises a second self-destruct pin whose activation disables the microcontroller, the second self-destruct pin connected with the tamper sensor.