Electronic component
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Abstract
The invention relates to an electronic component comprising an integrated circuit that is provided with a core with functional flip-flops. A part of the functional flip-flops are linked as input flip-flops with input pins of the component and a part of the functional flip-flops are linked as output flip-flops with output pins of the component. The aim of the invention is to fulfill high timing requirements while not complicating the verification of timing and logic. For this purpose, the input flip-flops and the output flip-flops are arranged in such a manner that they form at least input block and one output block each with respective clock domains that differ from the clock domains of the remaining core.
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Citations
28 Claims
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1-10. -10. (canceled)
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11. An electronic component with an integrated circuit, comprising:
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a plurality of input pins;
a plurality of output pins;
a core operatively connected to the integrated circuit, and subdivided into blocks that form different clock domains;
a plurality of functional flip-flops, a portion of the functional flip-flops connected as input flip-flops to input pins of the component and a portion of the functional flip-flops connected as output flip-flops to output pins of the component; and
whereby in normal operation inputs are entered into the electronic component via the input pins and the input flip-flops and whereby outputs of the electronic component are exported via the output flip-flops and the output pins; and
a remainder core adapted to provide the circuit elements of the input block, the remainder core and the output block adapted to provide the function of the integrated circuit, the remainder core forming a second clock domain that is different from the first and the third clock domain, wherein the input flip-flops form at least one input block having a first clock domain, and wherein the output flip-flops form an output block having a third clock domain, and wherein a built-in self-test BIST is performed so that the input flip-flops of the input block are interconnected to form a chain into which test vectors are input by a test pattern generator during the BIST, and the output flip-flops of the output block are interconnected to provide a linear feedback shift register and a test response evaluator for the BIST. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28)
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Specification