Low on resistance power MOSFET with variably spaced trenches and offset contacts
First Claim
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1. A MOS-gated semiconductor power device comprising:
- a semiconductor body having a first major surface and a second opposing major surface;
a base region of a first conductivity formed in said semiconductor body below said first major surface;
a first trench and a second trench formed in said semiconductor body, said first trench being spaced from said second trench by a first semiconductor region and a second semiconductor region, said first region being wider than said second region, and including access to said base region;
a gate structure formed in each of said trenches;
a conductive region of a second conductivity formed adjacent each of said trenches; and
an external contact in electrical contact with said conductive regions of said second conductivity and said base region at said first region.
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Abstract
A power semiconductor device of the trench variety in which the trenches follow a serpentine path.
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Citations
22 Claims
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1. A MOS-gated semiconductor power device comprising:
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a semiconductor body having a first major surface and a second opposing major surface;
a base region of a first conductivity formed in said semiconductor body below said first major surface;
a first trench and a second trench formed in said semiconductor body, said first trench being spaced from said second trench by a first semiconductor region and a second semiconductor region, said first region being wider than said second region, and including access to said base region;
a gate structure formed in each of said trenches;
a conductive region of a second conductivity formed adjacent each of said trenches; and
an external contact in electrical contact with said conductive regions of said second conductivity and said base region at said first region. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A MOS-gated semiconductor power device comprising:
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a silicon body having a first major surface and a second opposing major surface, and including a substrate portion and an epitaxial portion formed over a major surface of said substrate portion;
a base region of a first conductivity formed in said epitaxial portion below said first major surface of said silicon body;
a first trench and a second trench formed in said epitaxial portion, said first trench being spaced from said second trench by a first silicon region and a second silicon region, said first region being wider than said second region;
a gate structure formed in each of said trenches;
a conductive region of a second conductivity formed adjacent each of said trenches; and
an external contact in electrical contact with said conductive regions of said second conductivity and making electrical connection to said base region. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22)
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Specification