Method of making heterojunction P-I-N diode

• US 20050006729A1
• Filed: 08/10/2004
• Published: 01/13/2005
• Est. Priority Date: 05/03/2002
• Status: Active Grant

• Current Assignee: MACOM Technology Solutions Holdings, Inc.
• Original Assignee: David Russell Hoag, James Joseph Brogle, Timothy Edward Boles
• Inventors: Hoag, David Russell, Brogle, James Joseph, Boles, Timothy Edward
• Granted Patent: US 7,049,181 B2
• Time in Patent Office: Days
• US Class Current: 257/656
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 29/20 including, apart from doping materials or other impurities, only AIIIBV compounds
• CPC Class Codes: H01L 29/868 PIN diodes
• CPC Class Codes: Y02E 10/548 Amorphous silicon PV cells

Abstract

A heterojunction P—I—N diode switch comprises a first layer of doped semiconductor material of a first doping type, a second layer of doped semiconductor material of a second doping type and a substrate on which is disposed the first and second layers. An intrinsic layer of semiconductor material is disposed between the first layer and second layer. The semiconductor material composition of at least one of the first layer and second layer is sufficiently different from that of the intrinsic layer so as to form a heterojunction therebetween, creating an energy barrier in which injected carriers from the junction are confined by the barrier, effectively reducing the series resistance within the I region of the P—I—N diode and the insertion loss relative to that of homojunction P—I—N diodes.

Claims

1. A heterojunction P—

I—

N diode comprising;

a first layer of doped semiconductor material of a first doping type;

a second layer of doped semiconductor material of a second doping type;

a substrate on which is disposed the first and second layers; and

an intrinsic layer of semiconductor material disposed between the first layer and second layer, the semiconductor material composition of the intrinsic layer being different from that of at least the first layer so as to form a heterojunction therebetween.

2. The diode of claim 1, wherein the first layer of doped semiconductor material has an energy bandgap sufficiently greater than an energy bandgap of the intrinsic layer of semiconductor material for enhancing forward injection of carriers from the first layer to the intrinsic layer while retarding back injection of oppositely charged carriers from the intrinsic layer to the first layer, thereby effectively reducing the series resistance within the intrinsic layer of the diode.

3. The diode of claim 1, wherein the first layer comprises an anode electrode and the second layer comprises a cathode electrode.

4. The diode of claim 1, wherein the first layer comprises a layer of AlGaAs and wherein the intrinsic layer comprises a layer of GaAs.

5. The diode of claim 4, wherein the first layer is p-type and wherein the second layer is n-type.

6. The diode of claim 5, wherein the first layer has a thickness of about 0.8 microns and the second layer has a thickness of about 2 microns.

7. The diode of claim 5, wherein the aluminum composition of the first layer is at least 5 percent of the total number of aluminum plus gallium atoms.

8. The diode of claim 1, wherein the intrinsic layer semiconductor material composition is different from that of the second layer so as to form a heterojunction between the intrinsic layer and the second layer.

9. The diode of claim 8, wherein the first layer and second layers each comprise a layer of AlGaAs and wherein the intrinsic layer comprises a layer of GaAs.

10. A semiconductor P—

I—

N heterojunction device for use in a switch, comprising;

a first layer of aluminum gallium arsenide (AlGaAs) semiconductor material of a first doping type;

a second layer of a semiconductor material of a second doping type; and

an intrinsic layer of semiconductor material of gallium arsenide (GaAs) coupled between the first and second layers.

11. The device of claim 10, wherein the first layer, the second layer and the intrinsic layer are grown on a semiconductor substrate.

12. The device of claim 10, wherein the second layer of semiconductor material is GaAs.

13. The device of claim 12, wherein the GaAs second layer semiconductor material is n-type, the AlGaAs first layer is p-type, and wherein the GaAs second layer is grown on a GaAs semiconductor substrate and the intrinsic layer is grown on the GaAs second layer.

14. The device of claim 13, wherein the composition of aluminum in the first layer is at least 5 percent of the total number of aluminum plus gallium atoms.

15. The device of claim 12, wherein the GaAs second layer semiconductor material is p-type, the AlGaAs first layer is n-type, and wherein the AlGaAs first layer is grown on a GaAs semiconductor substrate and the intrinsic layer is grown on the AlGaAs first layer.

16. The device of claim 15, wherein the composition of aluminum in the first layer is at least 5 percent of the total number of aluminum plus gallium atoms.

17. The device of claim 10, wherein the second layer of semiconductor material is AlGaAs forming a double heterojunction.

18. The device of claim 17, wherein the AlGaAs second layer semiconductor material is n-type, the AlGaAs first layer is p-type, and wherein the AlGaAs second layer is grown on a GaAs semiconductor substrate and the intrinsic layer is grown on the AlGaAs second layer.

19. The device of claim 18, wherein the composition of aluminum in each of the first and second layers is at least 5 percent of the total number of aluminum plus gallium atoms.

20. A method of forming a heterojunction P—

I—

N diode switch comprising;

forming a semi-insulating substrate;

forming on the substrate a first layer of doped semiconductor material of a first doping type to form a cathode layer;

forming an intrinsic layer of semiconductor material on the first layer; and

forming a second layer of doped semiconductor material of a second doping type on the intrinsic layer to form an anode layer,

wherein at least one of the first layer and second layer is formed of semiconductor material different from that of the intrinsic layer to create a heterojunction therebetween, thereby providing an energy barrier.

21. The method of claim 20, wherein the first layer, second layer and intrinsic layer are formed at a same temperature.

22. The method of claim 21, wherein the same temperature is between 600 and 700 degrees celsius.

23. The method of claim 21, wherein the same temperature is approximately 650 degrees celsius.

24. The method of claim 21, wherein the step of forming the cathode layer comprises epitaxially growing on the substrate a first layer of n-type GaAs.

25. The method of claim 21, wherein the step of forming the anode layer comprises epitaxially growing on the intrinsic layer a second layer of p-type AlGaAs.

26. The method of claim 21, wherein at least one of the first layer and second layer of doped semiconductor materials has an energy bandgap greater than an energy bandgap of the intrinsic layer.