Dynamic circuits having improved noise tolerance and method for designing same

• US 20050007153A1
• Filed: 05/17/2004
• Published: 01/13/2005
• Est. Priority Date: 05/22/2003
• Status: Active Grant

• Current Assignee: Board of Regents of the University of Michigan (University of Michigan)
• Original Assignee: Board of Regents of the University of Michigan (University of Michigan)
• Inventors: Ding, Li, Mazumder, Pinaki
• Granted Patent: US 7,088,143 B2
• Time in Patent Office: Days
• US Class Current: 326/98
• CPC Class Codes: H03K 19/0963 using transistors of complementary type H03K19/0966 takes precedence

Abstract

A number of different dynamic circuits having improved noise tolerance and a method for designing same are provided. The circuits include a power supply node and a precharge node. Keeper circuitry is connected to the nodes and has a current-voltage characteristic that exhibits a negative differential resistance property to improve noise tolerance of the circuits.

Claims

1. A method for designing keeper circuitry for dynamic circuits, the method comprising:

providing a keeper circuitry description wherein keeper circuitry described by the keeper circuitry description has a circuit path through the keeper circuitry;

substantially maximizing peak current along the circuit path to improve noise tolerance of the dynamic circuit; and

substantially minimizing average current along the circuit path to reduce performance overhead due to the keeper circuitry.

2. The method as claimed in claim 1, wherein the circuitry includes a pair of crossed-coupled transistors.

3. The method as claimed in claim 1, wherein the circuitry includes a device which has an AC current-voltage characteristic that exhibits a negative differential resistance property.

4. The method as claimed in claim 3, wherein the device is a two-terminal device.

5. The method as claimed in claim 4, wherein the two-terminal device is a diode.

6. The method as claimed in claim 5, wherein the diode is a tunneling diode.

7. The method as claimed in claim 6, wherein the tunneling diode is a resonant tunneling diode.

8. The method as claimed in claim 3, wherein the device is a three-terminal device.

9. The method as claimed in claim 8, wherein the three-terminal device is a transistor.

10. The method as claimed in claim 9, wherein the transistor is a resonant tunneling transistor.

11. The method as claimed in claim 9, wherein the circuitry includes an inverter connected to the transistor.

12. The method as claimed in claim 4, wherein the circuitry includes a transistor connected to the two-terminal device.

13. The method as claimed in claim 12, wherein the circuitry includes an inverter connected to the transistor.

14. The method as claimed in claim 3, wherein the device is a resonant tunneling device.

15. In a dynamic circuit having a power supply node and a precharge node, the improvement comprising:

circuitry connected to the nodes wherein the circuitry has an AC current-voltage characteristic between the nodes that exhibits a negative differential resistance property to improve noise tolerance of the circuit.

16. A circuit comprising:

a dynamic combinational or sequential logic circuit having a precharge node; and

a keeper circuit having a first terminal connected to the precharge node and a second terminal connected to a power supply network, the keeper circuit;

having no current between the first and second terminals when the voltage across the keeper circuit is zero;

having no current between said first and second terminals when the voltage across the keeper circuit is a power supply voltage; and

having an AC current-voltage characteristic between the first and second terminals that has one or more negative differential resistance regions.

17. The circuit of claim 16, where the second terminal of the keeper circuit is connected to a ground network.

18. A circuit comprising:

a dynamic combinational or sequential logic circuit having a precharge node; and

a keeper circuit having a first terminal connected to the precharge node, a second terminal connected to a power supply network, and a third control terminal, the keeper circuit;

having no current between the first and second terminals when the voltage across the keeper circuit is zero;

having no current between the first and second terminals when the third control terminal is at a predefined voltage level; and

having an AC current-voltage characteristic between the first and second terminals that has one or more negative differential resistance regions.

19. The circuit of claim 18, where the second terminal of the keeper circuit is connected to a ground network.

20. A circuit comprising:

a dynamic combinational or sequential logic circuit having a precharge node; and

a keeper circuit connected between the precharge node and a power supply network, the keeper circuit comprising;

a two-terminal NDR device having a first terminal connected to the precharge node and a second terminal connected to a first internal node; and

a field-effect transistor having a first terminal connected to the first internal node, a second terminal connected to a power supply node, and a third terminal connected to a second internal node.

21. The circuit of claim 20, wherein the NDR device is a tunnel diode.

22. The circuit of claim 20, wherein the NDR device is a resonant tunneling diode.

23. The circuit of claim 20, further comprising an inverter having an input connected to the precharge node and an output connected to the second internal node.

24. The circuit of claim 23, wherein the NDR device is a tunnel diode.

25. The circuit of claim 23, wherein the NDR device is a semiconductor device having a negative differential resistance property.

26. A circuit comprising:

a dynamic combinational or sequential logic circuit having a precharge node; and

a keeper circuit connected between the precharge node and a power supply network, the keeper circuit comprising;

a three-terminal NDR device having a first terminal connected to the precharge node and a second terminal connected to a power supply node.

27. The circuit of claim 26, wherein the NDR device is a resonant tunneling transistor.

28. The circuit of claim 26, wherein the keeper circuit includes an inverter having an input connected to the precharge node and an output connected to an internal node.

29. The circuit of claim 28, wherein the NDR device has a third terminal connected to the internal node.

30. The circuit of claim 26, wherein the NDR device has a third terminal connected to an output of the circuit.

31. The circuit of claim 30, wherein the NDR device is a semiconductor device having a negative differential resistance property.

32. A circuit comprising:

a dynamic combinational or sequential logic circuit having a precharge node; and

a keeper circuit connected between the precharge node and a power supply network, the keeper circuit comprising;

a first field effect transistor having a first terminal connected to the precharge node, a second terminal connected to an internal node, and a third terminal connected to the power supply network; and

a second field-effect transistor having a first terminal connected to the internal node, a second terminal connected to the power supply network, and a third terminal connected to the precharge node.

33. The circuit of claim 32, wherein the third terminal of said first field-effect transistor is connected to a ground node of the network.

34. The circuit of claim 32, wherein the third terminal of the first field-effect transistor is connected to a constant voltage source.