Cascode circuit and integrated circuit having it

• US 20050007200A1
• Filed: 06/23/2004
• Published: 01/13/2005
• Est. Priority Date: 07/09/2003
• Status: Active Grant

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Inoue, Akira, Goto, Seiki
• Granted Patent: US 7,071,786 B2
• Time in Patent Office: Days
• US Class Current: 330/311
• CPC Class Codes: H03F 1/223 with MOSFET's
• CPC Class Codes: H03F 3/189 High-frequency amplifiers, e.g. radio frequency amplifiers

Abstract

A cascode circuit includes a first field effect transistor which has a source terminal grounded, a second field effect transistor which has a source terminal connected to a drain terminal of the first field effect transistor, and a first capacitor connected between the source terminal of the first field effect transistor and a gate terminal of the second field effect transistor. The first field effect transistor and the second field effect transistor are cascode-connected successively. A capacitance value of the first capacitor is 0.01 to 10 times that between the gate and source terminals of the second field effect transistor.

Claims

1. A cascode circuit comprising:

a first field effect transistor which has a source terminal grounded;

a second field effect transistor which has a source terminal connected to a drain terminal of said first field effect transistor; and

a first capacitor connected between the source terminal of said first field effect transistor and a gate terminal of said second field effect transistor,

wherein said first field effect transistor and said second field effect transistor are cascode-connected successively; and

a capacitance value of said first capacitor is 0.01 to 10 times that between the gate and source terminals of said second field effect transistor.

2. The cascode circuit according to claim 1, further comprising:

a first resistor connected between the source terminal of said first field effect transistor and the gate terminal of said second field effect transistor; and

a second resistor connected between the gate terminal of said second field effect transistor and a drain terminal of said second field effect transistor.

3. The cascode circuit according to claim 2, wherein a resistance value of said first resistor-per a gate width of 1 mm of said second field effect transistor is larger than 0.1 kΩ

and smaller than 120 kΩ

.

9. The cascode circuit according to claim 2, wherein the resistance values of said first and second resistors are set such that a voltage between the drain and source terminals of said first field effect transistor is equal to that between the drain and source terminals of said second field effect transistor.

11. The cascode circuit according to claim 1, further comprising:

a first resistor connected between a gate terminal of said first field effect transistor and the gate terminal of said second field effect transistor; and

a second resistor connected between the gate terminal of said second field effect transistor and a drain terminal of said second field effect transistor.

4. A cascode circuit comprising:

n field effect transistors, where n is a positive integer equal to or larger than three, wherein said n field effect transistors include;

a first field effect transistor having a source terminal grounded; and

n−

1 field effect transistors, wherein an m-th field effect transistor having a source terminal connected to a drain terminal of an (m−

1)-th field effect transistor, where m is a positive integer between 2 and n;

said n field effect transistors being cascode-connected successively; and

n−

1 capacitors, wherein an (m−

1)-th capacitor connected between the source terminal of said first field effect transistor and a gate terminal of said m-th field effect transistor; and

a capacitance value of said first capacitor is 0.01 to 10 times that between the gate and source terminals of said second field effect transistor.

5. The cascode circuit according to claim 4, further comprising n resistors which include:

a first resistor connected between the source terminal of said first field effect transistor and the gate terminal of said second field effect transistor;

n−

2 resistors, wherein a k-th resistor connected between a gate terminal of said k-th field effect transistor and a gate terminal of said (k+1)-th field effect transistor, where k is a positive integer between 2 and n−

1; and

an n-th resistor connected to the gate terminal of said n-th field effect transistor and a drain terminal of said n-th field effect transistor.

6. The cascode circuit according to claim 5, wherein a resistance value of said p-th resistor per a gate width of 1 mm of said (p+1)-th field effect transistor is larger than 0.1 kΩ

and smaller than 120 kΩ

, where p is a positive integer between 1 and n−

1.

7. The cascode circuit according to claim 4, wherein a capacitance value of said k-th capacitor is smaller than that of said (k−

1)-th capacitor, where k is a positive integer between 2 and n−

1.

8. The cascode circuit according to claim 7, wherein said n field effect transistors have the same capacitance values between the gate and source terminals thereof and the same mutual conductance values, and

said p-th capacitor has a capacitance value of Cgs/{(pg_mRL/n)−

1}, where Cgs is a capacitance value between the gate and source terminals of each of said n field effect transistors, g_m is a mutual conductance value of each of said n field effect transistors, RL is a value of a load resistance of said cascode circuit, and p is a positive integer between 1 and n−

1.

10. The cascode circuit according to claim 5, wherein the resistance values of said n resistors are set such that voltages between the drain and the source terminals of said n field effect transistors become equal to one another.

12. The cascode circuit according to claim 4, further comprising n resistors which include:

a first resistor connected between a gate terminal of said first field effect transistor and the gate terminal of said second field effect transistor;

n−

2 resistors, wherein k-th resistor connected between a gate terminal of said k-th field effect transistor and a gate terminal of said (k+1)-th field effect transistor, where k is a positive integer between 2 and n−

1; and

an n-th resistor connected to the gate terminal of said n-th field effect transistor and a drain terminal of said n-th field effect transistor.

13. An integrated circuit comprising at least one cascode circuit, wherein each of said at least one cascode circuit includes:

a first field effect transistor which has a source terminal grounded;

a second field effect transistor which has a source terminal connected to a drain terminal of said first field effect transistor; and

a first capacitor connected between the source terminal of said first field effect transistor and a gate terminal of said second field effect transistor;

said first field effect transistor and said second field effect transistor are cascode-connected successively; and

a capacitance value of said first capacitor is 0.01 to 10 times that between the gate and source terminals of said second field effect transistor;

wherein said integrated circuit includes;

at least one source electrode region capable of being connected to the outside of said integrated circuit;

at least one drain electrode region capable of being connected to the outside of said integrated circuit;

a field effect transistor region which includes a source electrode of said first field effect transistor of each of said at least one cascode circuit, a gate electrode of said first field effect transistor thereof, a gate electrode of said second field effect transistor thereof, and a drain electrode of said second field effect transistor thereof; and

a single capacitor region which corresponds to said first capacitor of each of said at least one cascode circuit;

wherein said at least one source electrode region, said at least one drain electrode region, said field effect transistor region, and said single capacitor region are provided on a semiconductor substrate;

each of at least one source electrode of said field effect transistor region and each of at least one drain electrode thereof are electrically connected to said at least one source electrode region and said at least one drain electrode region, respectively; and

said single capacitor region is disposed in the vicinity of said field effect transistor region.

14. The integrated circuit according to claim 13, wherein each of said at least one cascode circuit further comprises:

a first resistor connected between the source terminal of said first field effect transistor and the gate terminal of said second field effect transistor; and

a second resistor connected between the gate terminal of said second field effect transistor and a drain terminal of said second field effect transistor;

said integrated circuit further comprises;

two resistor regions which correspond to said first resistor of each of said at least one cascode circuit and said second resistor of each of them, said two resistor regions being provided on the semiconductor substrate; and

said two resistor regions being disposed in the vicinity of said field effect transistor region.

17. The integrated circuit according to claim 13, wherein said field effect transistor region is disposed between said at least one source electrode region and said at least one drain electrode region;

and

said single capacitor region is disposed adjacent to at least one source electrode of said field effect transistor region.

19. The integrated circuit according to claim 13, wherein each of at least one source electrode of said field effect transistor region and each of at least one drain electrode thereof are arranged alternately;

at least one of said at least one source electrode is disposed between said single capacitor region and either said at least one source electrode region or said at least one drain electrode region; and

a direction in which each of said at least one source electrode of said field effect transistor region and each of said at least one drain electrode thereof are arranged alternately is perpendicular to a direction in which said single capacitor region and either said at least one source electrode region or said at least one drain electrode region are opposed to each other.

21. The integrated circuit according to claim 13, wherein said single capacitor region comprises a plurality of partial capacitor regions, said plurality of partial capacitor regions are disposed in the vicinity of said field effect transistor region.

23. The integrated circuit according to claim 21, wherein each of at least one source electrode of said field effect transistor region and each of at least one drain electrode thereof are arranged alternately;

at least one of said at least one source electrode is disposed between each of said plurality of partial capacitor regions and either said at least one source electrode region or said at least one drain electrode region; and

a direction in which each of said at least one source electrode of said field effect transistor region and each of said at least one drain electrode thereof are arranged alternately is perpendicular to a direction in which each of said plurality of partial capacitor regions and either said at least one source electrode region or said at least one drain electrode region are opposed to each other.

25. The integrated circuit according to claim 13, wherein at least one source electrode and at least one drain electrode of said field effect transistor region are rectangular electrodes;

each of said at least one source electrode and each of said at least one drain electrode are arranged alternately in a direction perpendicular to a longer side of the rectangular shape;

a direction in which each of said at least one source electrode and each of said at least one drain electrode are arranged alternately is in parallel to a direction in which said field effect transistor region and said at least one drain electrode region are opposed to each other;

said at least one drain electrode of said field effect transistor region is connected to said at least drain electrode region by an air bridge.

28. The integrated circuit according to claim 13, wherein each of said at least one source electrode of said field effect transistor region and each of said at least one drain electrode thereof are alternately arranged;

and

an ion implantation region is provided between each of said at least one source electrode and each of said at least one drain electrode, as a connector which connects said first field effect transistor and second field effect transistor of each of said at least one cascode circuit successively.

31. The integrated circuit according to claim 13, wherein a part of said gate electrode of said first field effect transistor and a part of said gate electrode of said second field effect transistor are provided between each of at least one source electrode of said field effect transistor region and each of at least one drain electrode thereof;

and

the part of said gate electrode of said first field effect transistor and the part of said gate electrode of said second field effect transistor are disposed closer to said each of at least one source electrode than said each of at least one drain electrode.

34. The integrated circuit according to claim 13, wherein each of said at least one source electrode of said field effect transistor region and each of said at least one drain electrode thereof are alternately arranged;

a part of said gate electrode of said first field effect transistor and a part of said gate electrode of said second field effect transistor are provided between each of at least one source electrode of said field effect transistor region and each of at least one drain electrode thereof; and

a length of the part of said gate electrode of said first field effect transistor is longer than that of the part of said gate electrode of said second field effect transistor in the direction which is parallel to a direction in which each of said at least one source electrode and each of said at least one drain electrode are alternately arranged.

15. An integrated circuit comprising at least one cascode circuit, wherein each of said at least one cascode circuit includes:

n field effect transistors, where n is a positive integer equal to or larger than three, wherein said n field effect transistors include;

a first field effect transistor having a source terminal grounded; and

n−

1 field effect transistors, wherein an m-th field effect transistor having a source terminal connected to a drain terminal of an (m−

1)-th field effect transistor, where m is a positive integer between 2 and n;

said n field effect transistors being cascode-connected successively; and

n−

1 capacitors, wherein an (m−

1)-th capacitor connected between the source terminal of said first field effect transistor and a gate terminal of said m-th field effect transistor; and

a capacitance value of said first capacitor is 0.01 to 10 times that between the gate and source terminals of said second field effect transistor;

wherein said integrated circuit includes;

at least one source electrode region capable of being connected to the outside of said integrated circuit;

at least one drain electrode region capable of being connected to the outside of said integrated circuit;

a field effect transistor region which includes a source electrode of said first field effect transistor of each of said at least one cascode circuit, a gate electrode of said q-th field effect transistor thereof, and a drain electrode of said n-th field effect transistor thereof, where q is a positive integer between 1 and n; and

n−

1 capacitor regions which correspond to said n−

1 capacitors of each of said at least one cascode circuit;

said at least one source electrode region, said at least one drain electrode region, said field effect transistor region, and said n−

1 capacitor regions are provided on a semiconductor substrate;

each of at least one source electrode and each of at least one drain electrode of said field effect transistor region are electrically connected to said at least one source electrode region and said at least one drain electrode region, respectively; and

said n−

1 capacitor regions are disposed in the vicinity of said field effect transistor region.

16. The integrated circuit according to claim 15, wherein each of said at least one cascode circuit further comprise:

n resistors which include;

a first resistor connected to the source terminal of said first field effect transistor and the gate terminal of said second field effect transistor;

n−

2 resistors, wherein a k-th resistor connected between a gate terminal of said k-th field effect transistor and a gate terminal of said. (k+1)-th field effect transistor, where k is a positive integer between 2 and n−

1; and

an n-th resistor connected to a gate terminal of said n-th field effect transistor and a drain terminal of said n-th field effect transistor;

wherein said integrated circuit further includes n resistor regions which correspond to said n resistors of each of said at least one cascode circuit, said n resistor regions being provided on the semiconductor substrate, and said n resistor regions being disposed in the vicinity of said field effect transistor region.

18. The integrated circuit according to claim 15, wherein said field effect transistor region is disposed between said at least one source electrode region and said at least one drain electrode region;

and

at least one of said n−

1 capacitor regions are disposed adjacent to at least one source electrode of said field effect transistor region.

20. The integrated circuit according to claim 15, wherein each of at least one source electrode of said field effect transistor region and each of at least one drain electrode thereof are arranged alternately;

at least one of said at least one source electrode is disposed between each of said n−

1 capacitor regions and either said at least one source electrode region or said at least one drain electrode region; and

a direction in which each of said at least one source electrode of said field effect transistor region and each of said at least one drain electrode thereof are arranged alternately is perpendicular to a direction in which each of said n−

1 capacitor regions and either said at least one source electrode region or said at least one drain electrode region are opposed to each other.

22. The integrated circuit according to claim 15, wherein each of said n−

1 capacitor regions comprises a plurality of partial capacitor regions, said plurality of partial capacitor regions are disposed in the vicinity of said field effect transistor region.

24. The integrated circuit according to claim 22, wherein each of at least one source electrode of said field effect transistor region and each of at least one drain electrode thereof are arranged alternately;

at least one of said at least one source electrode is disposed between each of said plurality of partial capacitor regions and either said at least one source electrode region or said at least one drain electrode region; and

a direction in which each of said at least one source electrode of said field effect transistor region and each of said at least one drain electrode thereof are arranged alternately is perpendicular to a direction in which each of said plurality of partial capacitor regions and either said at least one source electrode region or said at least one drain electrode region are opposed to each other.

26. The integrated circuit according to claim 15, at least one source electrode and at least one drain electrode of said field effect transistor region are rectangular electrodes;

each of said at least one source electrode and each of said at least one drain electrode are arranged alternately in a direction perpendicular to a longer side of the rectangular shape;

a direction in which each of said at least one source electrode and each of said at least one drain electrode are arranged alternately is in parallel to a direction in which said field effect transistor region and said at least one drain electrode region are opposed to each other;

said at least one drain electrode of said field effect transistor region is connected to said at least drain electrode region by an air bridge.

29. The integrated circuit according to claim 15, wherein each of said at least one source electrode of said field effect transistor region and each of said at least one drain electrodes thereof are alternately arranged;

and

n−

1 ion implantation regions are provided between each of said at least one source electrode and said at least one drain electrode, as connectors which connect said n field effect transistors of each of said at least one cascode circuit with one other.

33. The integrated circuit according to claim 15, wherein a part of said gate electrode of said q-th field effect transistor is provided between each of at least one source electrode of said field effect transistor region and each of at least one drain electrode thereof, where q is a positive integer between 1 and n;

and

the part of said gate electrode of said q-th field effect transistor is disposed closer to said each of at least one source electrode than said at least one drain electrode.

36. The integrated circuit according to claim 15, wherein each of said at least one source electrode of said field effect transistor region and each of said at least one drain electrodes thereof are alternately arranged;

a part of said gate electrode of said q-th field effect transistor is provided between each of at least one source electrode of said field effect transistor region and each of at least one drain electrode thereof, where q is a positive integer between 1 and n; and

a length of the part of said gate electrode of said first field effect transistor is longer than lengths of the parts of said gate electrodes of the field effect transistors other than said first field effect transistor in the direction which is parallel to a direction in which each of said at least one source electrode and each of said at least one drain electrode are alternately arranged.

27. The integrated circuit having a plurality of cascode circuits, wherein each of said plurality of cascode circuit comprises:

a first field effect transistor which has a source terminal grounded;

a second field effect transistor which has a source terminal connected to a drain terminal of said first field effect transistor; and

a first capacitor connected between the source terminal of said first field effect transistor and a gate terminal of said second field effect transistor;

wherein said first field effect transistor and said second field effect transistor are cascode-connected successively; and

a capacitance value of said first capacitor is 0.01 to 10 times that between the gate and source terminals of said second field effect transistor;

said integrated circuit comprises;

a plurality of source electrode regions capable of being connected to the outside of said integrated circuit;

a plurality of drain electrode regions capable of being connected to the outside of said integrated circuit;

a plurality of field effect transistor regions each of which includes source and gate electrodes of said first field effect transistor of at least one of said plurality of cascode circuits, and gate and drain electrodes of said second field effect transistor of at least one of them; and

a plurality of capacitor regions each of which corresponds to said first capacitor of each of said plurality of cascode circuits;

said plurality of source regions, said plurality of drain regions, said plurality of field effect transistor regions, and said plurality of capacitor regions are provided on a semiconductor substrate;

said integrated circuit comprising a plurality of cell assemblies each of which includes one of said plurality of source electrode regions, one of said plurality of drain electrode regions, one of said plurality of field effect transistor regions, and one of said plurality of capacitor regions;

said capacitor region and said source electrode region are opposed to each other in each of said plurality of cell assemblies;

said field effect transistor region is arranged between said capacitor region and said source electrode region in each of said plurality of cell assemblies;

a direction in which said drain electrode region and said field effect transistor region are opposed to each other is perpendicular to that in which said capacitor region and said source electrode region are opposed to each other in each of said plurality of cell assemblies; and

said capacitor region of each of said a plurality of cell assemblies is connected to said source electrode region of an adjacent cell assembly.

30. The integrated circuit according to claim 27, wherein each of at least one source electrode and each of at least one drain electrode of said field effect transistor region of each of said cell assemblies are alternately arranged;

and

an ion implantation region is provided between each of said at least one source electrode and each of said at least one drain electrode, as a connector which connects said first field effect transistor and second field effect transistor of each of said at least one cascode circuit successively.

32. The integrated circuit according to claim 27, wherein a part of said gate electrode of said first field effect transistor and a part of said gate electrode of said second field effect transistor are provided between each of at least one source electrode of each of said plurality of field effect transistor regions and each of at least one drain electrode thereof;

and

the part of said gate electrode of said first field effect transistor and the part of said gate electrode of said second field effect transistor are disposed closer to said each of at least one source electrode than said each of at least one drain electrode.

35. The integrated circuit according to claim 27, wherein each of at least one source electrode and each of at least one drain electrode of said field effect transistor region of each of said cell assemblies are alternately arranged;

a part of said gate electrode of said first field effect transistor and a part of said gate electrode of said second field effect transistor are provided between each of at least one source electrode of each of said plurality of field effect transistor regions and each of at least one drain electrode thereof; and

a length of the part of said gate electrode of said first field effect transistor is longer than that of the part of said gate electrode of said second field effect transistor in the direction which is parallel to a direction in which each of said at least one source electrode and each of said at least one drain electrode are alternately arranged.