Liquid crystal display device and fabrication method thereof

• US 20050007507A1
• Filed: 06/30/2004
• Published: 01/13/2005
• Est. Priority Date: 05/12/2000
• Status: Abandoned Application

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Ono, Kikuo, Oke, Ryutaro, Nakayoshi, Yoshiaki, Kaneko, Toshiki
• Application Number:
  US10/879,635
• Publication Number:
  US 20050007507A1
• Time in Patent Office: Days
• US Class Current: 349/38
• CPC Class Codes: G02F 1/134363 for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
• CPC Class Codes: G02F 1/13458 Terminal pads
• CPC Class Codes: G02F 1/136213 Storage capacitors associated with the pixel electrode
• CPC Class Codes: G02F 1/136227 Through-hole connection of the pixel electrode to the active element through an insulation layer
• CPC Class Codes: G02F 1/136236 using a grey or half tone lithographic process
• CPC Class Codes: G02F 1/13629 Multilayer wirings
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask

Abstract

The present invention provides a novel photolithography processes using photoresist pattern having at least two areas which has different thickness from each other for a fabrication method for a liquid crystal display device having reversed staggered and channel-etched type thin film transistors, reduce a number of photolithography processes required for whole of the fabrication process of the liquid crystal display device, and improve brightness of the liquid crystal display device.

Claims

1. A liquid crystal display device comprising:

a pair of substrates;

a liquid crystal layer interposed between said pair of substrates;

a plurality of drain wiring lines and a plurality of gate wiring lines being formed one of said pair of substrates;

at least one pixel is composed in respective regions surrounded by said drain wiring lines and said gate wiring lines;

a lower electrode, a dielectric film, a protective film, and an upper electrode being formed at location corresponding to said at least one pixel in this order;

a semiconductor layer formed between said dielectric film and said protective film;

a contact hole is provided by perforating said protective film, and

said upper electrode contacts with said semiconductor layer through said contact hole.

2. A liquid crystal display device according to claim 1,

wherein said upper electrode is a transparent electrode.

3. A liquid crystal display device according to claim 1,

wherein at least one transistor is formed in said one pixel.

4. A liquid crystal display device according to claim 3,

wherein said upper electrode is electrically connected to said transistor.

5. A liquid crystal display device according to claim 3,

wherein said dielectric film is a gate insulating layer of said transistor.

6. A liquid crystal display device according to claim 3,

wherein said lower electrode is composed of the same material as a gate electrode of said transistor.