Self-regulating interconnect structure

• US 20050008010A1
• Filed: 07/09/2004
• Published: 01/13/2005
• Est. Priority Date: 07/10/2003
• Status: Abandoned Application

• Current Assignee: Interactic Holdings LLC
• Original Assignee: Interactic Holdings LLC
• Inventors: Reed, Coke S.
• Application Number:
  US10/887,762
• Publication Number:
  US 20050008010A1
• Time in Patent Office: Days
• US Class Current: 370/360
• CPC Class Codes: H04L 12/56 Packet switching systems
• CPC Class Codes: H04L 49/15 Interconnection of switching modules
• CPC Class Codes: H04L 49/25 Routing or path finding in a switch fabric
• CPC Class Codes: H04L 49/3072 Packet splitting
• CPC Class Codes: H04L 49/358 Infiniband Switches
• CPC Class Codes: H04L 49/50 Overload detection or protection within a single switching element

Abstract

An interconnect device includes a data switch and a control switch coupled in parallel between multiple input lines and a plurality of output ports. The interconnect device comprises an input logic element coupled between the multiple input lines and the data switch. The input logic element can receive a data stream composed of ordered data segments, insert the data segments into the data switch, and regulate data segment insertion to delay insertion of a data segment subsequent in order until a signal is received designating exit from the data switch of a data segment previous in order.

Claims

1. An interconnect structure comprising:

a data switch capable of communicating data from a plurality of input lines to a plurality of output lines;

a plurality of output switches coupled between the data switch and the plurality of output lines; and

a control switch coupled between the plurality of input lines and the plurality of output lines in parallel with the data switch and capable of regulating data flow to prevent overloading of the output switches and ensure that data exits the interconnect structure to the output lines in the order of entry through the input lines.

2. The interconnect structure according to claim 1 further comprising:

a plurality of data switches communicating data from the plurality of input lines to the plurality of output lines.

3. The interconnect structure according to claim 2 further comprising:

a plurality of control switches coupled between the plurality of input lines and the plurality of output lines in parallel with the plurality of data switches and selectively regulating data among the plurality of data switches.

4. The interconnect structure according to claim 1 wherein:

the data switch is an unscheduled switch.

5. The interconnect structure according to claim 1 wherein the data switch and the control switch are multiple-level minimum-logic network interconnect structures, the data switch for transferring data and the control switch for regulating the data switch.

6. The interconnect structure according to claim 1 further comprising:

at least one input logic element coupled between the plurality of input lines and the data switch, the at least one input logic element being capable of receiving a data stream composed of ordered data segments, inserting the data segments into the data switch, and regulating data segment insertion to delay insertion of a data segment subsequent in order until a signal is received designating exit from the data switch of a data segment previous in order.

7. The interconnect structure according to claim 6 wherein:

the at least one input logic element configures the data into a data structure including a header with a leading bit set to one indicating data presence, a binary address of a target output switch following the leading bit, a binary address of a target input logic element, and a single bit set to one following the binary addresses; and

the data switch removes the binary address of the target output switch during traversal of the data switch by arrival of the leading bit at the target output switch.

8. The interconnect structure according to claim 7 wherein:

the target output switch sends a control packet to the control switch that comprises the leading bit set to one, the binary address of the target input logic element, and a payload of the single bit set to one;

the control switch transfers the control packet to the target input logic element; and

the target input logic element, upon receipt of the payload, unlocks a control lock enabling a next data packet segment to enter the data switch.

9. The interconnect structure according to claim 6 further comprising:

an auxiliary switch coupled between the control switch and the at least one input logic element.

10. The interconnect structure according to claim 6 wherein:

the at least one input logic element is capable of dividing a data packet into a plurality of fixed length data segments, attaching a header to a segment, sending the data segments with header to the data switch, and controls timing of adjacent serial data segments to ensure correct ordering.

11. The interconnect structure according to claim 10 wherein:

the at least one input logic element sends a preceding data segment of pair of adjacent-time data segments to the data switch, sets a lock preventing application of a following data segment of the adjacent-time segment pair, and sustaining the lock until the at least one input logic element receives a signal indicating the preceding segment has reached a target output switch.

12. The interconnect structure according to claim 11 wherein:

the at least one input logic element sets and enforces a delay between segments of adjacent-time segment pairs.

13. The interconnect structure according to claim 6 further comprising:

an auxiliary switch coupled between the control switch and the at least one input logic element, the auxiliary switch comprising a plurality of cross-bar switches.

14. The interconnect structure according to claim 1 further comprising:

a control line from an external device to the data switch that carries a control signal preventing data transmission from the data switch to the external device via a target output switch.

15. The interconnect structure according to claim 1 further comprising:

a concentrator coupled to the control switch that converts a larger number of relatively lightly-loaded lines to a smaller number of relatively heavily-loaded lines.

16. The interconnect structure according to claim 1 further comprising:

a plurality of first-in, first-out FIFO buffers coupled between the plurality of output switches and the control switch, the FIFO buffers having multiple different lengths with various length control packets applied to the FIFO buffers according to length whereby control segments enter the control switch without time overlaps or gaps.

17. The interconnect structure according to claim 1 wherein the data switch further comprises:

a plurality of node arrays arranged in multiple interconnected rows and levels;

a plurality of permutation elements coupling node arrays on a level; and

a plurality of first-in, first-out (FIFO) delay lines coupled on the levels and recircling to form a closed-loop on a level.

18. The interconnect structure according to claim 17 further comprising:

a logic unit coupled to the plurality of input logic elements; and

a plurality of control lines coupling the FIFO delay lines via the logic unit to the plurality of input logic elements and capable of indicating presence of data on a level that has not progressed to a subsequent level whereby the input logic elements can delay injection of data into the data switch and avoid collision.

19. A data structure for usage as a header for a data segment in an interconnect structure comprising a data switch coupled to multiple input lines via a plurality of input ports and coupled to multiple output lines via a plurality of output ports, the interconnect structure further comprising a control switch coupled between the multiple input lines and the multiple output lines in parallel with the data switch, the data structure comprising:

a leading bit set to one indicating data presence;

a binary address of a target output port following the leading bit;

a binary address of a target input port; and

a single bit set to one following the binary addresses.

20. The data structure according to claim 19 further comprising:

a payload field following the single bit.

21. The data structure according to claim 19 further comprising:

for an interconnect structure having a plurality of data lines into an input port of the plurality of input ports, a binary identifier designating a selected data line of the target input port.

22. The data structure according to claim 19 wherein:

the target input port is the input port that sends the data segment to the target output port.

23. An interconnect device for usage in an interconnect structure that includes a data switch and a control switch coupled in parallel between multiple input lines and a plurality of output ports, the interconnect device comprising:

an input logic element coupled between the multiple input lines and the data switch, the input logic element being capable of receiving a data stream composed of ordered data segments, inserting the data segments into the data switch, and regulating data segment insertion to delay insertion of a data segment subsequent in order until a signal is received designating exit from the data switch of a data segment previous in order.

24. The interconnect device according to claim 23 wherein:

the input logic element configures the data into a data structure including a header with a leading bit set to one indicating data presence, a binary address of a target output port following the leading bit, a binary address of a target input logic element, and a single bit set to one following the binary addresses.

25. The interconnect device according to claim 24 wherein:

the target output switch sends a control packet to the control switch that comprises the leading bit set to one, the binary address of the target input logic element, and a payload of the single bit set to one;

the control switch transfers the control packet to the target input logic element; and

the target input logic element, upon receipt of the payload, unlocks a control lock enabling a next data packet segment to enter the data switch.

26. The interconnect device according to claim 23 wherein:

the input logic element is capable of dividing a data packet into a plurality of fixed length data segments, attaching a header to a segment, sending the data segments with header to the data switch, and controls timing of adjacent serial data segments to ensure correct ordering.

27. The interconnect device according to claim 26 wherein:

the input logic element sends a preceding data segment of pair of adjacent-time data segments to the data switch, sets a lock preventing application of a following data segment of the adjacent-time segment pair, and sustaining the lock until the at least one input logic element receives a signal indicating the preceding segment has reached a target output switch.

28. The interconnect device according to claim 27 wherein:

the input logic element sets and enforces a delay between segments of adjacent-time segment pairs.