METHOD OF FORMING SHALLOW TRENCH ISOLATION USING DEEP TRENCH ISOLATION

• US 20050009290A1
• Filed: 07/09/2003
• Published: 01/13/2005
• Est. Priority Date: 07/09/2003
• Status: Active Grant

• Current Assignee: Polaris Innovations Limited (Wi-LAN Inc.)
• Original Assignee: Infineon Technologies AG
• Inventors: Yan, Jiang, Shum, Danny Pak-Chum
• Granted Patent: US 6,864,151 B2
• Time in Patent Office: Days
• US Class Current: 438/424
• CPC Class Codes: H01L 21/76229 Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
• CPC Class Codes: H01L 21/763 Polycrystalline semiconductor regions H01L21/76264 takes precedence

Abstract

A method of isolating active areas of a semiconductor workpiece. Deep trenches are formed in a workpiece between adjacent first active areas, and an insulating layer and a semiconductive material are deposited in the deep trenches. The semiconductive material is recessed below a top surface of the workpiece. Shallow trenches are formed in the workpiece between adjacent second active areas, and an insulating material is deposited in the shallow trenches and in the semiconductive material recess. The deep trenches may also be formed between an adjacent first active area and second active area. The first active areas may be high voltage devices, and the second active areas may be low voltage devices. The shallow trench isolation over the recessed semiconductive material in the deep trenches is self-aligned.

Claims

1. A method of forming isolating regions of a semiconductor device, the method comprising:

providing a workpiece, the workpiece having at least one first region and at least one second region, the workpiece having a top surface;

forming at least one first active area in said at least one first region;

patterning the first region with at least one first trench after said step of forming said first active area, the first trench having sidewalls, a bottom, and a first width and a first depth within the workpiece;

forming a first insulating layer over the at least one first trench sidewalls and bottom;

depositing a semiconductive material in the at least one first trench over the first insulating layer;

depositing a photo resist for patterning shallow second trenches over said first and second regions of said substrate;

patterning both said first and second regions each region patterned with at least one second trench, the second trench having a second depth within the workpiece, that is less than the first depth and a second width greater than said first width, said second trenches in said first region being located over said first trenches so as to recess said first insulating layer adding semiconductor material in said first trenches;

depositing an insulating material in the at least one second trench and in the semiconductive material recess of the at least one first trench; and

then forming at least one second active area in the second region.

2. The method according to claim 1, wherein the at least one first active area comprises at least one high voltage device, and wherein the at least one second active area comprises at least one low voltage device.

4. The method according to claim 1, wherein depositing a semiconductive material comprises depositing doped polysilicon or undoped polysilicon, wherein forming the insulating layer over the at least one first trench sidewalls and bottom comprises:

forming a thin nitride layer over the at least one first trench sidewalls and bottom; and

forming a thin oxide layer over the thin nitride layer.

5. The method according to claim 1, further comprising, before depositing an insulating material in the at least one second trench and in the semiconductive material recess of the at least one first trench, depositing a second insulating layer over the at least one second trench and over the semiconductive material recess of the at least one first trench.

6. The method according to claim 5, wherein depositing the second insulating layer comprises:

forming a thin silicon dioxide layer over the at least one second trench and over the semiconductive material recess of the at least one first trench; and

forming a thin silicon nitride layer over the thin silicon dioxide layer.

3. (Canceled)

7. (Cancelled)

8. (Cancelled)

9. (Cancelled)

10. A method of forming isolating regions of a semiconductor device, the method comprising:

providing a workpiece, the workpiece having at least one first region and at least one second region, the workpiece having a top surface;

forming at least one high voltage active area in said at least one first region;

patterning the first region with at least one deep trench after forming said at least one high voltage active area, the deep trench having a first width, sidewalls, a bottom, and a first depth within the workpiece;

forming a first insulating layer over the at least one deep trench sidewalls and bottom;

depositing a semiconductive material in the at least one deep trench over the first insulating layer;

recessing said semiconductive material beneath the workpiece top surface;

forming a hard mask having portions over said at least one first region and over said at least one second region;

patterning the portion of said hard mask over said at least one second region and transferring said hard mask pattern to form at least one shallow trench in said second region and leaving the portion of said hard mask over said first region in place such that said first region is not further patterned, the shallow trench having a second depth and a second width within the workpiece, wherein the second depth is less than the first depth and the second width is greater than said first width;

removing any remaining hard mask from over at least one first region and said at least one second region;

depositing an insulating material in the at least one shallow trench and in the semiconductive material recess of the at least one deep trench; and

forming at least one low voltage active region in the second region.

11. The method according to claim 10, wherein depositing an insulating material in the semiconductive material recess of the at least one deep trench comprises forming shallow trench isolation over the deep trenches.

12. The method according to claim 10, wherein depositing the semiconductive material comprises depositing doped polysilicon or undoped polysilicon, wherein forming the insulating layer over the at least one deep trench sidewalls and bottom comprises:

forming a thin nitride layer over the at least one deep trench sidewalls and bottom; and

forming a thin oxide layer over the thin nitride layer.

13. The method according to claim 10, further comprising, before depositing an insulating material in the at least one shallow trench and in the semiconductive material recess of the at least one deep trench, depositing a second insulating layer over the at least one shallow trench and over the semiconductive material recess of the at least one deep trench.

14. The method according to claim 13, wherein depositing the second insulating layer comprises:

forming a thin oxide layer over the at least one shallow trench and over the semiconductive material recess of the at least one deep trench; and

forming a thin nitride layer over the thin silicon dioxide layer.

18. The method according to claim 10, wherein patterning the first region with at least one deep trench comprises:

depositing a hard mask over the workpiece top surface;

patterning the hard mask with the deep trench pattern;

patterning the workpiece using the hard mask as a mask; and

removing the hard mask.

19. The method according to claim 18, wherein depositing the hard mask comprises depositing Boron-doped Silicon Glass (BSG).

20. The method according to claim 10, wherein said steps of forming a hard mask and patterning the hard mask over said at least one second region with at least one shallow trench comprising the steps of:

depositing a photoresist over the hard mask;

patterning the photoresist with the at least one shallow trench pattern;

patterning the hard mask with the photoresist pattern;

removing the photoresist;

patterning the workpiece using the hard mask as a mask; and

removing the hard mask.

21. The method according to claim 20, wherein depositing the hard mask comprises depositing high density plasma (HDP) silicon dioxide.

25. The method according to claim 10 wherein said at least one low voltage active region in the second region is formed after said insulating material is deposited in the at least one shallow trench and the at least one deep trench.

26. The method according to claim 10 wherein said at least one low voltage region in the second region is formed prior to said step of patterning the first region with at least one deep trench.

15. (Cancelled)

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17. (Cancelled)

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24. (Cancelled)