Manufacturing method for semiconductor device

• US 20050009313A1
• Filed: 06/04/2004
• Published: 01/13/2005
• Est. Priority Date: 06/06/2003
• Status: Abandoned Application

• Current Assignee: Sanyo Electric Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Sanyo Electric Company Limited (Panasonic Holdings Corporation)
• Inventors: Imai, Kenji, Suzuki, Nobuhiro
• Application Number:
  US10/861,337
• Publication Number:
  US 20050009313A1
• Time in Patent Office: Days
• US Class Current: 438/611
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/02 Bonding areas; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/02371 connecting the bonding area on a surface of the semiconductor or solid-state body with another surface of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/02377 Fan-in arrangement
• CPC Class Codes: H01L 2224/05001 Internal layers
• CPC Class Codes: H01L 2224/05008 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
• CPC Class Codes: H01L 2224/05024 the internal layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05139 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/05144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05181 Tantalum [Ta] as principal constituent
• CPC Class Codes: H01L 2224/05184 Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05569 the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05639 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05647 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05655 : Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05666 : Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05681 : Tantalum [Ta] as principal constituent
• CPC Class Codes: H01L 2224/05684 : Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/06135 : Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
• CPC Class Codes: H01L 2224/13 : of an individual bump connector
• CPC Class Codes: H01L 2224/13024 : the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13099 : Material
• CPC Class Codes: H01L 23/3114 : the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 24/02 : Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/10 : Bump connectors bumps on insulating substrates, e.g. chip carriers, H01L23/49816; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/14 : Integrated circuits

Abstract

An internal wire is formed via an oxide film on the front surface of a semiconductor substrate so as to extend toward the boundary relative to an adjacent integrated circuit region. An upper supporting base is fixedly formed on the front surface of the semiconductor substrate by means of a resin layer of epoxy adhesive or the like, and a lower supporting base is fixedly formed on the back surface of the semiconductor substrate by means of a resin layer of epoxy adhesive or the like, whereby a laminated body is formed. The resin layer and the internal wire are partially removed, leaving a portion of the laminated body, to thereby form an inverted-V shaped groove (a cut-off groove) where a part of the internal wire is exposed to the outside. Thereafter, the resulting cut-off groove is exposed to plasma atmosphere to thereby dissolve, and thus remove, any remaining resin fragments attached to the exposed end portion of the internal wire.

Claims

1. A method for manufacturing a semiconductor device, comprising:

a first step of fixedly forming a supporting base on a semiconductor substrate having an internal wire formed thereon, via a resin layer, whereby a laminated body is formed on the semiconductor substrate;

a second step of removing at least a part of the resin layer and a part of the internal wire, while leaving a part of the laminated body, to thereby form a groove where a part of the internal wire is exposed to the outside;

a third step of exposing the groove formed in the laminated body to plasma atmosphere for cleaning;

a fourth step of forming a metal film covering a surface of the laminated body and the groove; and

a fifth step of patterning the metal film into an outside wire,

wherein

the plasma atmosphere is plasma atmosphere capable of etching the resin layer.

5. The method for manufacturing a semiconductor device according to claim 1, wherein

the plasma atmosphere comprises O₂ plasma or CF₄ plasma.

2. A method for manufacturing a semiconductor device, comprising:

a first step of forming an integrated circuit in each region defined by a scribe line on a front surface of a semiconductor substrate and forming an internal wire extending toward a boundary relative to an adjacent integrated circuit region;

a second step of fixedly forming an upper supporting base on the front surface of the semiconductor substrate via a first insulating resin layer so as to cover an area where the integrated circuit is formed;

a third step of removing the semiconductor substrate along the scribe line and fixedly forming a lower supporting base on a back surface of the semiconductor substrate via a second insulating resin layer, whereby a laminated body is formed on the back surface of the semiconductor substrate;

a fourth step of forming a groove along the scribe line, where a part of the second insulating resin and a part of the internal wire are exposed to the outside, while leaving a part of the upper supporting base;

a fifth step of exposing the groove formed in the laminated body to plasma atmosphere for cleaning;

a sixth step of forming a metal film covering the back surface of the semiconductor substrate and the groove;

a seventh step of patterning the metal film into an outside wire; and

an eighth step of cutting the upper supporting base to thereby divide the laminated body into individual semiconductor devices,

wherein

the plasma atmosphere is plasma atmosphere capable of etching resin forming the second insulating resin layer.

4. The method for manufacturing a semiconductor device according to claim 2, wherein

the integrated circuit formed on the front surface of the semiconductor device is a light receiving element, and the upper supporting base is a transparent supporting base.

6. The method for manufacturing a semiconductor device according to claim 2, wherein

the plasma atmosphere comprises O₂ plasma or CF₄ plasma.

8. The method for manufacturing a semiconductor device according to claim 4, wherein

the plasma atmosphere comprises O₂ plasma or CF₄ plasma.

3. A method for manufacturing a semiconductor device, comprising:

a first step of forming an integrated circuit in each region defined by a scribe line on a front surface of a semiconductor substrate and forming an internal wire extending toward a boundary relative to an adjacent integrated circuit region;

a second step of fixedly forming an upper supporting base on the front surface of the semiconductor substrate via a first insulating resin layer so as to cover an area where the integrated circuit is formed;

a third step of forming a groove along the scribe line, where a part of the first insulating resin layer and a part of the internal wire are exposed to outside, while leaving a part of the semiconductor substrate;

a fourth step of exposing the groove to plasma atmosphere for cleaning;

a fifth step of forming a metal film covering the front surface of the semiconductor substrate and the groove;

a sixth step of patterning the metal film into an outside wire;

a seventh step of removing the semiconductor substrate along the scribe line and fixedly forming a lower supporting base on a back surface of the semiconductor substrate via a second insulating resin layer, whereby a laminated body is formed on the back surface of the semiconductor substrate; and

an eighth step of cutting the lower supporting base to thereby divide the laminated body into individual semiconductor devices, wherein

the plasma atmosphere is a plasma atmosphere capable of etching resin forming the first insulating resin layer.

7. The method for manufacturing a semiconductor device according to claim 3, wherein

the plasma atmosphere comprises O₂ plasma or CF₄ plasma.