Method and system for single chip satellite set-top box system

• US 20050009481A1
• Filed: 11/18/2003
• Published: 01/13/2005
• Est. Priority Date: 07/11/2003
• Status: Active Grant

• Current Assignee: Broadcom Corporation (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Bushner, Paige
• Granted Patent: US 7,526,245 B2
• Time in Patent Office: Days
• US Class Current: 455/132
• CPC Class Codes: H04N 21/426 Internal components of the client ; Characteristics thereof H04N5/44 takes precedence
• CPC Class Codes: H04N 21/4263 involving specific tuning arrangements, e.g. two tuners
• CPC Class Codes: H04N 21/42684 Client identification by a unique number or address, e.g. serial number, MAC address, socket ID network arrangements, protocols or services for addressing or naming H04L61/00

Abstract

Certain embodiments of the invention may be found in an single chip satellite set-top box solution that comprises demodulation, decoding and audio/video display functions integrated within a single chip. The single chip solution for the satellite set-top box is adapted to provide demodulation, display, and other related set-top box functions for a system that may be adapted to handle two incoming data streams modulated using an 8PSK, 8PSK-turbo or QPSK scheme, for example. Accordingly, the single chip satellite set-top box solution comprise dual 8 PSK/8 PSK-turbo/QPSK demodulators, a MIPS CPU, a 16-bit DDR-SDRAM, graphics display capability for handling two channels, and audio/video decoders and DACs for handling two incoming channels. The single chip satellite set-top box solution may also comprise integrated peripheral support for major set top box functions including a smart card interface, IR receivers, and general purpose input/output (GP/IO) pins.

Claims

1. A system for an integrated set-top box, the system comprising:

a single integrated circuit chip comprising;

a first satellite receiver demodulator integrated within said single integrated circuit chip;

at least a second satellite receiver demodulator integrated within said single integrated circuit chip; and

at least one processor integrated within said single integrated circuit chip and coupled to said first satellite receiver demodulator and said second satellite receiver demodulator.

2. The system according to claim 1, wherein said at least one processor comprises a MIPS processor, a floating point processor and at least one data transport processor.

3. The system according to claim 1, further comprising a programmable memory integrated within said single integrated circuit chip.

4. The system according to claim 3, wherein said programmable memory stores at least one of security information and configuration information for said single integrated circuit chip.

5. The system according to claim 4, wherein said security information comprises at least one of a security key and a device identifier (ID)

6. The system according to claim 5, wherein said device identifier comprises at least one of an electronic serial number and an address.

7. The system according to claim 4, wherein said configuration information comprises at least one of configuration data and code for configuring said single integrated circuit chip.

8. The system according to claim 3, wherein said programmable memory is a one-time programmable memory.

9. The system according to claim 1, further comprising at least one video decoder integrated within said single integrated circuit chip and coupled to said at least one processor.

10. The system according to claim 9, wherein said at least one video decoder is a standard definition MPEG-2 video decoder.

11. The system according to claim 9, further comprising at least one video and graphics display engine integrated within said single integrated circuit chip and coupled to said at least one video decoder.

12. The system according to claim 11, further comprising at least one video encoder integrated within said single integrated circuit chip and coupled to said at least one video and graphics display engine.

13. The system according to claim 12, further comprising at least one video digital-to-analog converter and RF modulator integrated within said single integrated circuit chip and coupled to said at least one video encoder.

14. The system according to claim 1, further comprising at least one audio decoder integrated within said single integrated circuit chip and coupled to said at least one processor.

15. The system according to claim 14, wherein said at least one audio decoder is an MPEG-2 audio decoder.

16. The system according to claim 14, further comprising at least one audio digital-to-analog converter integrated within said single integrated circuit chip and coupled to said at lest one audio decoder.

17. The system according to claim 1, further comprising at least one memory controller integrated within said single integrated circuit chip and coupled to at least said at least one processor.

18. The system according to claim 17, wherein said at least one memory controller comprises a unified dual data rate DRAM memory controller.

19. The system according to claim 1, further comprising a digital satellite equipment control (DiSEqC) bus integrated within said single integrated circuit chip.

20. The system according to claim 1, further comprising at least one of a plurality of peripheral interfaces comprising, an infrared interface, a universal asynchronous receiver/transmitter, a serial peripheral interface, a binary synchronous communication interface, general purpose input/output pins, and pulse width modulation controller interface, integrated within said single integrated circuit chip.

21. The system according to claim 1, further comprising at least one read-only memory integrated within said single integrated circuit chip.

22. The system according to claim 21, wherein said at least one read-only memory comprises a CPU boot ROM and a FLASH.

23. The system according to claim 1, further comprising at least one debug port integrated within said single integrated circuit chip.

24. The system according to claim 23, wherein said debug port comprises a JTAG port or any variation thereof.

25. The system according to claim 1, further comprising at least one card reader or writer interface integrated within said single integrated circuit chip.

26. The system according to claim 25, wherein said card reader or writer interface is a smart card reader or writer interface.

27. The system according to claim 1, further comprising at least one core voltage regulator integrated within said single integrated circuit chip.

28. The system according to claim 1, further comprising at least one phase lock loop integrated within said single integrated circuit chip.

29. The system according to claim 1, further comprising at least one telephony modem integrated within said single integrated circuit chip.

30. The system according to claim 1, wherein said first satellite receiver demodulator and said second satellite receiver demodulator are at least one of 8 PSK, 8 PSK-turbo and QPSK demodulators.

31. A method for processing information in a set-top box, the system comprising:

receiving a first modulated signal by a first satellite receiver within a single integrated circuit chip;

demodulating said first modulated signal by said first satellite receiver within said single integrated circuit chip to generate a first demodulated signal;

receiving a second modulated signal by a second satellite receiver within said single integrated circuit chip; and

demodulating said second modulated signal by said second satellite receiver within said single integrated circuit chip to generate a second demodulated signal.

32. The method according to claim 31, further comprising decoding within said single integrated circuit chip, a video portion of said first demodulated signal to generate a first decoded video signal.

33. The method according to claim 32, further comprising encoding within said single integrated circuit chip, said first decoded video signal within said single integrated circuit chip to generate a first encoded digital video signal.

34. The method according to claim 33, further comprising converting within said single integrated circuit chip, said first encoded digital video signal to a first analog video signal.

35. The method according to claim 31, further comprising decoding within said single integrated circuit chip, an audio portion of said first demodulated signal to generate a first decoded digital audio signal.

36. The method according to claim 35, further comprising converting within said single integrated circuit chip, said first decoded digital audio signal to a first analog audio signal.

37. The method according to claim 31, further comprising decoding within said single integrated circuit chip, a video portion of said second demodulated signal to generate a second decoded video signal.

38. The method according to claim 37, further comprising encoding within said single integrated circuit chip, said second decoded video signal within said single integrated circuit chip to generate a second encoded digital video signal.

39. The method according to claim 38, further comprising converting within said single integrated circuit chip, said second encoded digital video signal to a second analog video signal.

40. The method according to claim 37, further comprising decoding within said single integrated circuit chip, an audio portion of said second demodulated signal to generate a second decoded digital audio signal.

41. The method according to claim 40, further comprising converting within said single integrated circuit chip, said second decoded digital audio signal to a second analog audio signal.

42. The method according to claim 31, wherein said demodulating of said first modulated signal and said demodulating of said second modulated signal occurs simultaneously.