Synchronization of timestamps to compensate for communication latency between devices

• US 20050010691A1
• Filed: 06/30/2004
• Published: 01/13/2005
• Est. Priority Date: 06/30/2003
• Status: Active Grant

• Current Assignee: Viavi Solutions, Inc. (Lumentum Holdings Inc.)
• Original Assignee: Viavi Solutions, Inc. (Lumentum Holdings Inc.)
• Inventors: Lawson, Arthur Michael, Oyadomari, Randy
• Granted Patent: US 8,190,722 B2
• Time in Patent Office: Days
• US Class Current: 709/248
• CPC Class Codes: H04B 7/26 at least one of which is mobile
• CPC Class Codes: H04J 3/0682 by delay compensation, e.g. by compensation of propagation delay or variations thereof, by ranging
• CPC Class Codes: H04J 3/0685 Clock or time synchronisation in a node; Intranode synchronisation
• CPC Class Codes: H04L 43/00 Arrangements for monitoring or testing data switching networks
• CPC Class Codes: H04L 43/0852 Delays
• CPC Class Codes: H04L 43/106 using time related information in packets, e.g. by adding timestamps
• CPC Class Codes: H04L 43/18 Protocol analysers
• CPC Class Codes: H04L 7/0041 Delay of data signal

Abstract

Protocol analyzer systems enable synchronization of timestamps and the capture of data across serially chained boxes that are used together to monitor and capture network data. Through experiment, it can be determined how long it takes to propagate a signal to each box in the chain. These values are then recorded in each box in a delay register so that each box has a recorded delay value corresponding to the time required to propagate a signal to or receive a signal from every other box. Each box applies a control signal, such as a run signal or a trigger signal, to the ports in the box only after the expiration of the delay value indicated in the delay register. The box initiating the signal has the largest delay since the other boxes need to get the signal before the boxes can begin to operate with a common counter, with successive boxes having smaller delays.

Claims

1. In a system that includes a plurality of boxes, wherein each box includes one or more blades and each blade has one or more ports, a method for synchronizing activity within the ports of the domain, the method comprising:

generating a control signal at a first box that implements a selected activity at each of a first port and a second port, wherein the first port is located in the first box and the second port is located in the a second box;

receiving the control signal at the second box; and

referring to a delay register in the first box in order to select a period of time to delay before implementing the action designated by the control signal, whereby delaying the period of time designated by the delay register ensures that the selected activity is implemented at the first box and at the second box at substantially the same time.

2. A method as defined in claim 1, wherein the control signal includes one or more of a run signal, a stop signal, and a trigger signal.

3. The method as in claim 1, wherein the control signal triggers a first capture buffer in communication with the first port and a second capture buffer in communication with the second port to each capture a selected portion of the communications traffic received through each port.

4. A method as defined in claim 1, further comprising, prior to generating a control signal at a first box, detecting a trigger event at a particular port, wherein the trigger signal is asserted.

5. The method as in claim 1, further comprising delivering the control signal using a serial protocol, wherein a field programmable gate array at each box analyzes the serial protocol to identify which ports the control signal is directed to.

6. The method as in claim 1, further comprising generating a clock signal in a master box and propagating the clock signal to at least one additional box via cables that are in communication with each box.

7. The method as in claim 1, wherein the control signal is delivered using a serial protocol, wherein the control signals coordinate the operation of each of the first port and the second port.

8. The method as in claim 1, wherein:

each blade further comprises a capture buffer in communication with each port and the control signal comprises a trigger signal that is generated at a port when the port'"'"'s associated capture buffer is full; and

the trigger signal is propagated to each port in the domain and acts to stop the capture of data in the capture buffer associated with each port in the domain.

9. The method as in claim 1, wherein:

the control signal comprises a run signal delivered using a serial protocol to place each of the first port and the second port in a run mode whereby;

communications traffic is received through each of the first port and the second port and routed to analyzer modules in communication with each of the first port and the second port; and

the communications traffic is monitored by the analyzer modules to identify data of interest.

10. A method as defined in claim 1, further comprising generating a clock signal in the first box and transmitting the clock signal to each of the first box and the second box, whereby a counter in each box runs at the rate of the clock signal, or a multiple of the rate of the clock signal.

11. A method as defined in claim 1, wherein the control signal includes a delay component that indicates a period of time that the second box should delay before implementing the selected activity.

12. In a protocol analyzer system in a computer network, a method for synchronously performing actions on each of multiple boxes within the protocol analyzer system, wherein each box includes one or more blades and each blade has one or more ports, the method comprising:

configuring a plurality of the ports from a plurality of the boxes in the protocol analyzer system into a domain, wherein at least two of the ports in the domain are located in different boxes;

generating a control signal at one of the ports in the domain, the control signal being capable of implementing a selected activity at each port in the domain;

propagating the control signal to each box having a port in the domain; and

referring to a delay register in each box having a port in the domain in order to identify a period of time to delay before implementing the action designated by the control signal, whereby delaying the period of time designated by the delay register ensures that the selected activity is synchronously implemented at each port in the domain.

13. A method as defined in claim 12, wherein the control signal includes one or more of a run signal, a stop signal, and a trigger signal.

14. A method as defined in claim 12, further comprising, prior to generating a control signal at a first box, detecting a trigger event at a port, wherein the control signal comprises a trigger signal.

15. The method as in claim 12, further comprising delivering the control signals using a serial protocol, wherein a field programmable gate array at each box analyzes the serial protocol to identify which ports the control signal is directed to.

16. The method as in claim 12, further comprising generating a clock signal in one of the boxes and propagating the clock signal to at least one additional box, wherein each box that generates or receives the clock signal has a counter that runs at the rate of the clock signal or a multiple of the rate of the clock signal, the clock signal used to generate time stamps in a capture buffer in communication with each port.

17. The method as in claim 12, wherein the control signal is delivered using a serial protocol, wherein the control signals coordinate the operation of each port in the domain of ports.

18. The method as in claim 12, wherein:

each blade further comprises a capture buffer in communication with each port and the control signal comprises a trigger signal that is generated at a port when the port'"'"'s associated capture buffer is full; and

the trigger signal is propagated to each port in the domain and acts to stop the capture of data in the capture buffer associated with each port in the domain.

19. The method as in claim 12, wherein the control signal comprises a run signal delivered using a serial protocol to place the domain of ports in a run mode whereby:

communications traffic is received through the domain of ports; and

the communications traffic is monitored by analyzer modules in communication with the domain of ports to identify data of interest.

20. In a protocol analyzer system in a computer network, a method for synchronously performing actions on each of a plurality of interconnected boxes within the protocol analyzer system, wherein each box includes one or more blades and each blade has one or more ports, the method comprising:

configuring a sync-group from among a plurality of interconnected boxes, wherein one of the boxes in the sync group comprises a master box and the remaining boxes comprise slave boxes;

generating a clock signal in the master box;

transmitting the clock signal to the slave boxes, wherein each box in the sync-group has a counter that is run at the rate of the clock signal or a multiple of the rate of the clock signal, wherein the counter is used to create time stamps in a capture buffer that captures selected portions of network traffic;

generating a run signal at the master box and transmitting the run signal to each box in the sync-group, the run signal starting a domain of ports distributed over the sync-group to monitor network traffic; and

referring to, a delay register in each box in the sync-group in order to identify a period of time to delay before running, whereby delaying the period of time designated by the delay register ensures that each box will synchronously start running.

21. A method as defined in claim 20, further comprising detecting a trigger event at a particular port and generating a control signal comprising a trigger signal.

22. A method as defined in claim 20, further comprising, prior to transmitting the clock signal, multiplying the clock signal in a clock multiplier to increase the frequency of the clock signal.

23. The method as in claim 20, further comprising delivering the run signal using a serial protocol, wherein a field programmable gate array at each box analyzes the serial protocol to identify which ports the run signal is directed to.

24. The method as in claim 20, wherein the run signal and the clock signal are generated at substantially the same time.

25. A protocol analyzer system for synchronously performing protocol analysis operations, the system comprising:

a sync-group of boxes, comprising;

a master box, comprising;

a clock for generating a clock signal for propagation to each box in the sync-group;

a counter for receiving the clock signal or a multiple of the clock signal and providing time stamps to selected data stored by the protocol analyzer system;

at least one blade, each blade comprising at least one port for receiving network traffic; and

a delay register containing a value representative of the communications delay between each box in the sync-group; and

at least one slave box, each slave box comprising;

a counter for receiving the clock signal from the master box and providing time stamps to selected data captured by the protocol analyzer system;

at least one blade, each blade comprising at least one port for receiving network traffic, wherein at least one of the ports on the master box and/or slave box(es) are configured in a domain; and

a delay register containing a value representative of the communications delay between each box in the sync-group;

whereby a control signal that is generated at one box in the sync-group is implemented at each box according to the delay register on each box so that the action designated by the control signal is substantially synchronously implemented at each port in the domain.

26. A system as in claim 25, wherein the master box and each slave box further comprise:

a field programmable gate array capable of analyzing a serial protocol, which comprises one or more control signals, to identify which of one or more control signals is applicable to the ports located on each box.

27. A system as in claim 25, wherein each blade further comprises:

a capture buffer for capturing network data of interest; and

an analyzer for monitoring network traffic and triggering the capture of network data of interest by generating a trigger control signal for transmission to each port in the domain.

28. A system as defined in claim 25, further comprising an analyzer which comprises:

a filter component, wherein the filter component is operable to monitor the network traffic to identify data of interest and direct the storage of the data of interest in a capture buffer; and

a trigger component, wherein the trigger component is operable to direct each port in the domain to capture a selected portion of the network traffic when the trigger component detects a triggering event.

29. A system as defined in claim 25, wherein the master and at least one slave box are interconnected by one or more dedicated cables for transmitting inter-box control signals.