System and method for identifying TLB entries associated with a physical address of a specified range

• US 20050010739A1
• Filed: 07/28/2003
• Published: 01/13/2005
• Est. Priority Date: 07/10/2003
• Status: Active Grant

• Current Assignee: Intellectual Ventures Funding LLC (Intellectual Ventures LLC)
• Original Assignee: Transmeta Corporation (Novafora, Inc.)
• Inventors: Dunn, David, Rozas, Guillermo, Klaiber, Alexander, Anvin, H. Peter
• Granted Patent: US 7,149,872 B2
• Time in Patent Office: Days
• US Class Current: 711/207
• CPC Class Codes: G06F 12/1054 the data cache being concurrently physically addressed

Abstract

A system and method for identifying a TLB entry having a physical address that is within a specified range are disclosed. The method includes obtaining a tentative TLB entry from a page table entry and accessing a physical address associated with the tentative TLB entry. The method further includes comparing the physical address of the tentative TLB entry with a predetermined range of addresses. If the physical address is within the finite range of addresses, an exception is invoked. In response to the exception, the physical address and/or an attribute of the tentative TLB entry can be modified. The tentative TLB entry can then be stored in a TLB.

Claims

1. A computer implemented method for creating a translation lookaside buffer entry comprising:

a) accessing a physical memory address associated with a tentative translation lookaside buffer entry;

b) comparing said physical memory address with a predetermined memory range; and

c) if said physical memory address is within said predetermined memory range, invoking an exception.

2. The method as described in claim 1 further comprising modifying said tentative translation lookaside buffer entry in response to said exception.

3. The method as described in claim 2 further comprising storing a modified translation lookaside buffer entry into a translation lookaside buffer.

4. The method as described in claim 1 further comprising if said physical memory address is outside said predetermined memory range, storing said tentative translation lookaside buffer entry into a translation lookaside buffer without modification.

5. The method as described in claim 3 further comprising if said physical memory address is outside said predetermined memory range, storing said tentative translation lookaside buffer entry into a translation lookaside buffer without said modifying.

6. The method as described in claim 1 wherein said tentative translation lookaside buffer entry is accessed from a page table entry.

7. The method as described in claim 2 wherein said physical memory address of said tentative translation lookaside buffer entry is modified by said modifying.

8. The method as described in claim 2 wherein an attribute of said tentative translation lookaside buffer entry is modified by said modifying.

9. A circuit for creating a translation lookaside buffer entry comprising:

a fill engine for constructing a tentative translation lookaside buffer entry and for invoking a comparison between a physical memory address associated with said tentative translation lookaside buffer entry and a predetermined physical memory address range;

a comparator coupled to said fill engine for comparing said physical memory address associated with said tentative translation lookaside buffer entry and said predetermined physical memory address range and for invoking an exception if a match occurs; and

a fix-up handler coupled to said fill engine and said comparator for handling said exception by performing an operation to modify said tentative translation lookaside buffer entry.

10. The circuit as recited in claim 9 further comprising a page table entry which provides said tentative translation lookaside buffer entry.

11. The circuit as described in claim 9 wherein said fix-up handler generates a modified tentative translation lookaside buffer entry.

12. The circuit as described in claim 11 wherein said fix-up handler modifies, the physical memory address of said tentative translation lookaside buffer entry.

13. The circuit as described in claim 11 wherein said fix-up handler modifies an attribute of said tentative translation lookaside buffer entry.

14. The circuit as described in claim 11 wherein said fill engine enters said modified translation lookaside buffer entry into a translation lookaside buffer.

15. A computer system comprising a processor coupled to a bus and a memory coupled to said bus and comprising instructions that when executed implement a method of creating a translation lookaside buffer entry comprising:

a) accessing a physical memory address associated with a tentative translation lookaside buffer entry;

b) comparing said physical memory address with a predetermined memory range;

c) if said physical address is within said predetermined memory range, invoking an exception.

16. The computer system as described in claim 15 wherein said method further comprises modifying said tentative translation lookaside buffer entry in response to said exception to generate a modified tentative translation lookaside buffer entry.

17. The computer system as described in claim 16 wherein said method further comprises storing said modified tentative translation lookaside buffer entry into a translation lookaside buffer.

18. The computer system as described in claim 15 wherein said method further comprises if said physical address is outside said predetermined memory range, storing said tentative translation lookaside buffer entry into a translation lookaside buffer without modification.

19. The computer system as described in claim 18 wherein if said physical address is outside said predetermined memory range, storing said tentative translation lookaside buffer entry into a translation lookaside buffer without modification.

20. The computer system as described in claim 15 wherein said method further comprises obtaining said tentative translation lookaside buffer entry from a page table entry.

21. The computer system as described in claim 16 wherein said physical address of said tentative translation lookaside buffer entry is modified by said modifying.

22. The computer system as described in claim 16 wherein an attribute of said tentative translation lookaside buffer entry is modified by said modifying.