Design-based monitoring
First Claim
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1. A method for monitoring fabrication of an integrated circuit (IC) on a semiconductor wafer, comprising:
- generating a product design profile (PDP) using an electronic design automation (EDA) tool, the PDP comprising an indication of a site in at least one layer of the IC that is susceptible to a process fault;
fabricating the at least one layer of the IC on the wafer; and
applying a process monitoring tool to perform a measurement at the site in the at least one layer responsively to the PDP.
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Abstract
A method for monitoring fabrication of an integrated circuit (IC) on a semiconductor wafer includes generating a product design profile (PDP) using an electronic design automation (EDA) tool, the PDP comprising an indication of a site in at least one layer of the IC that is susceptible to a process fault. Upon fabricating at least one layer of the IC on the wafer, a process monitoring tool is applied to perform a measurement at the site in at least one layer responsively to the PDP.
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Citations
82 Claims
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1. A method for monitoring fabrication of an integrated circuit (IC) on a semiconductor wafer, comprising:
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generating a product design profile (PDP) using an electronic design automation (EDA) tool, the PDP comprising an indication of a site in at least one layer of the IC that is susceptible to a process fault;
fabricating the at least one layer of the IC on the wafer; and
applying a process monitoring tool to perform a measurement at the site in the at least one layer responsively to the PDP. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method for monitoring fabrication of an integrated circuit (IC) on a semiconductor wafer, comprising:
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generating a product design profile (PDP) using an electronic design automation (EDA) tool, the PDP comprising an identification of a region in at least one layer of the IC that is characterized by a periodic pattern;
fabricating the at least one layer of the IC on the wafer; and
applying a process monitoring tool to perform a measurement in the region of the at least one layer responsively to the periodic pattern. - View Dependent Claims (12, 13, 14, 15)
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16. A method for monitoring fabrication of an integrated circuit (IC) on a semiconductor wafer, comprising:
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generating a product design profile (PDP) using an electronic design automation (EDA) tool, the PDP comprising an identification of a plurality of regions in at least one layer of the IC and a respective criticality parameter for each of the regions, indicative of a maximum tolerable defect size in each of the regions;
fabricating at least one layer of the IC on the wafer; and
applying a process monitoring tool to perform a measurement in one or more of the regions in at least one layer responsively to the respective criticality parameter. - View Dependent Claims (17, 18, 19)
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20. A method for monitoring fabrication of an integrated circuit (IC) on a semiconductor wafer, comprising:
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designing a layout of at least one layer of the IC using an electronic design automation (EDA) tool, at least one layer comprising a structure that is amenable to testing;
generating a product design profile (PDP) using the EDA tool, the PDP comprising information regarding the structure;
fabricating at least one layer of the IC on the wafer; and
applying a process monitoring tool to perform a measurement on the structure in at least one layer, responsively the information in the PDP. - View Dependent Claims (21, 22, 23, 24, 25)
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26. Apparatus for producing an integrated circuit (IC) on a semiconductor wafer, comprising:
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an electronic design automation (EDA) tool, which is adapted to generate a design of at least one layer of the IC and a product design profile (PDP), which comprises an indication of a site in at least one layer that is susceptible to a process fault;
a production tool, which is adapted to fabricate at least one layer of the IC on the wafer responsively to the design; and
a process monitoring tool, which is adapted to perform a measurement at the site in at least one layer responsively to the PDP. - View Dependent Claims (27, 28, 29, 30, 31, 32, 33, 34, 35)
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36. Apparatus for producing an integrated circuit (IC) on a semiconductor wafer, comprising:
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an electronic design automation (EDA) tool, which is adapted to generate a design of at least one layer of the IC and a product design profile (PDP), which comprises an identification of a region in at least one layer of the IC that is characterized by a periodic pattern;
a production tool, which is adapted to fabricate at least one layer of the IC on the wafer responsively to the design; and
a process monitoring tool, which is adapted to perform a measurement in the region in at least one layer responsively to the periodic pattern. - View Dependent Claims (37, 38, 39, 40)
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41. Apparatus for producing an integrated circuit (IC) on a semiconductor wafer, comprising:
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an electronic design automation (EDA) tool, which is adapted to generate a design of at least one layer of the IC and a product design profile (PDP), which comprises an identification of a plurality of regions in the at least one layer of the IC and a respective criticality parameter for each of the regions, indicative of a maximum tolerable defect size in each of the regions;
a production tool, which is adapted to fabricate at least one layer of the IC on the wafer responsively to the design; and
a process monitoring tool, which is adapted to perform a measurement in one or more of the regions responsively to the respective criticality parameter. - View Dependent Claims (42, 43, 44)
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45. Apparatus for producing an integrated circuit (IC) on a semiconductor wafer, comprising:
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an electronic design automation (EDA) tool, which is adapted to generate a design of at least one layer of the IC, the layout comprising a structure that is amenable to testing, and which is further adapted to generate and a product design profile (PDP), which comprises information regarding the structure;
a production tool, which is adapted to fabricate at least one layer of the IC on the wafer responsively to the design; and
a process monitoring tool, which is adapted to perform a measurement on the structure, responsively the information in the PDP. - View Dependent Claims (46, 47, 48, 49, 50)
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51. A computer software product for use in producing an integrated circuit (IC) on a semiconductor wafer, the product comprising a computer-readable medium in which program instructions are stored, the instructions comprising at least one of an electronic design automation (EDA) program component and a process monitoring program component,
wherein the EDA program component, when read by a computerized EDA tool, causes the EDA tool to generate a design of at least one layer of the IC and a product design profile (PDP), which comprises an indication of a site in at least one layer that is susceptible to a process fault, and wherein the process monitoring program component, when read by a computerized process monitoring tool after fabrication of at least one layer of the IC on the wafer responsively to the design, causes the process monitoring tool to perform a measurement at the site in at least one layer responsively to the PDP.
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61. A computer software product for use in producing an integrated circuit (IC) on a semiconductor wafer, the product comprising a computer-readable medium in which program instructions are stored, the instructions comprising at least one of an electronic design automation (EDA) program component and a process monitoring program component,
wherein the EDA program component, when read by a computerized EDA tool, causes the EDA tool to generate a design of at least one layer of the IC and a product design profile (PDP), which comprises an identification of a region in the at least one layer of the IC that is characterized by a periodic pattern, and wherein the process monitoring program component, when read by a computerized process monitoring tool after fabrication of at least one layer of the IC on the wafer responsively to the design, causes the process monitoring tool to perform a measurement in the region in at least one layer responsively to the periodic pattern.
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66. A computer software product for use in producing an integrated circuit (IC) on a semiconductor wafer, the product comprising a computer-readable medium in which program instructions are stored, the instructions comprising at least one of an electronic design automation (EDA) program component and a process monitoring program component,
wherein the EDA program component, when read by a computerized EDA tool, causes the EDA tool to generate a design of at least one layer of the IC and a product design profile (PDP), which comprises an identification of a plurality of regions in the at least one layer of the IC and a respective criticality parameter for each of the regions, indicative of a maximum tolerable defect size in each of the regions, and wherein the process monitoring program component, when read by a computerized process monitoring tool after fabrication of at least one layer of the IC on the wafer responsively to the design, causes the process monitoring tool to perform a measurement in one or more of the regions responsively to the respective criticality parameter.
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70. A computer software product for use in producing an integrated circuit (IC) on a semiconductor wafer, the product comprising a computer-readable medium in which program instructions are stored, the instructions comprising at least one of an electronic design automation (EDA) program component and a process monitoring program component,
wherein the EDA program component, when read by a computerized EDA tool, causes the EDA tool to generate a design of at least one layer of the IC, the layout comprising a structure that is amenable to testing, and a product design profile (PDP), which comprises information regarding the structure, and wherein the process monitoring program component, when read by a computerized process monitoring tool after fabrication of at least one layer of the IC on the wafer responsively to the design, causes the process monitoring tool to perform a measurement on the structure, responsively the information in the PDP.
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76. Apparatus for monitoring production of an integrated circuit (IC) on a semiconductor wafer, following fabrication of at least one layer of the IC on the wafer responsively to a design and a product design profile (PDP) generated by an electronic design automation (EDA) tool, the PDP including an indication of a site in at least one layer that is susceptible to a process fault, the apparatus comprising:
a process monitoring tool, which is adapted to perform a measurement at the site in at least one layer responsively to the PDP. - View Dependent Claims (77, 78, 79, 80, 81, 82)
Specification