Semiconductor device and manufacturing method thereof

• US 20050012122A1
• Filed: 08/18/2004
• Published: 01/20/2005
• Est. Priority Date: 08/29/2002
• Status: Abandoned Application

• Current Assignee: Fujitsu Limited, Sony Corporation (Sony Group Corp.)
• Original Assignee: Fujitsu Limited, Sony Corporation (Sony Group Corp.)
• Inventors: Tabuchi, Kiyotaka, Suzuki, Atsushi, Kakamu, Katsumi
• Application Number:
  US10/920,209
• Publication Number:
  US 20050012122A1
• Time in Patent Office: Days
• US Class Current: 257/257
• CPC Class Codes: H01L 21/02129 the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
• CPC Class Codes: H01L 21/02167 the material being a silicon carbide not containing oxygen, e.g. SiC, SiC:H or silicon carbonitrides H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/022 the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides adhesion layers or buffer layers H01L21/02304, H01L21/02362
• CPC Class Codes: H01L 21/02211 the compound being a silane, e.g. disilane, methylsilane or chlorosilane
• CPC Class Codes: H01L 21/02274 in the presence of a plasma [PECVD]
• CPC Class Codes: H01L 21/28123 Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
• CPC Class Codes: H01L 21/312 Organic layers, e.g. photoresist H01L21/3105, H01L21/32 take precedence; photoresists per se G03C
• CPC Class Codes: H01L 21/3127 Layers comprising fluoro (hydro)carbon compounds, e.g. polytetrafluoroethylene
• CPC Class Codes: H01L 21/3148 Silicon Carbide layers
• CPC Class Codes: H01L 21/76828 thermal treatment
• CPC Class Codes: H01L 21/76829 characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
• CPC Class Codes: H01L 21/76835 Combinations of two or more different dielectric layers having a low dielectric constant H01L21/76832 takes precedence
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 23/53295 Stacked insulating layers
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/12044 OLED

Abstract

A threshold voltage change and degradation of the drain saturation current over a period of time of a MOS transistor are prevented by providing a permeable insulating film that serves as an inter-layer etching stopper layer on the surface of a plug, and an inter-layer insulating film that can be made from a low dielectric constant organic insulating film.

Claims

1-7. -7. (canceled).

8. A manufacturing method of a semiconductor device, containing a MOS transistor formed on a semiconductor substrate, and a multilayer wiring structure formed on the semiconductor substrate and connected to the MOS transistor, comprising:

a step for forming an inter-layer insulating film on the semiconductor substrate,

a step for forming a permeable insulating film on the inter-layer insulating film, and

a heat-treatment process at a temperature of 200 degrees C. or higher.

9. The manufacturing method of the semiconductor device as claimed in claim 8, wherein the permeable insulating film is a silicon carbide film.

10. The manufacturing method of the semiconductor device as claimed in claim 8, further comprising a step for polishing a wiring layer that constitutes the multilayer wiring structure by a chemical mechanical polishing method, the step being provided between the step for forming the inter-layer insulating film, and the step for forming the permeable insulating film on the inter-layer insulating film.

11. The manufacturing method of the semiconductor device as claimed in claim 8, wherein the inter-layer insulating film is a low dielectric constant organic film.

12. The manufacturing method of the semiconductor as claimed in claim 8, wherein the inter-layer insulating film is constituted by a layer of a low dielectric constant organic film and an inorganic insulating film.

13. The manufacturing method of the semiconductor device as claimed in claim 11, wherein the low dielectric constant organic film is constituted by one of a hydrocarbon polymer and a fluorinated aromatic polymer.

14. The manufacturing method of the semiconductor device as claimed in claim 8, wherein a silicon nitride film is formed such that a side wall insulating film of a gate electrode of the MOS transistor is covered.

15. The manufacturing method of the semiconductor device as claimed in claim 8, wherein a conductive pattern formed in the inter-layer insulation film contains Cu.