Method for forming silicon film with changing grain size by thermal process

• US 20050012136A1
• Filed: 07/16/2003
• Published: 01/20/2005
• Est. Priority Date: 07/16/2003
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Huang, Chih Yuan, Chen, Jonason
• Granted Patent: US 6,872,972 B2
• Time in Patent Office: Days
• US Class Current: 257/315
• CPC Class Codes: H01L 21/0245 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/4925 with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with only a vertical doping structure or vertical doping variation H01L29/4916

Abstract

Roughly described, a silicon layer transitions from polysilicon at one surface to amorphous silicon at the opposite surface. The transition can be monotonic, and can be either continuous or it can change abruptly from polysilicon to amorphous silicon. If such a layer is formed as the floating gate of a floating gate transistor structure, the larger grain structure adjacent to the tunnel dielectric layer reduces the formation of a tip (protrusion) and thus reduces leakage. On the other hand, the smaller grain structure adjacent to the gate dielectric layer produces a smooth, more uniform gate dielectric layer. The polysilicon-to-amorphous silicon transistor can be fabricated with a temperature profile that favors polysilicon formation at the start of floating gate deposition, and transitions during deposition to a temperature that favors amorphous silicon deposition at the end of floating gate deposition.

Claims

1. A multi-layer assembly comprising:

a first silicon layer comprising at least first and second surfaces, and further comprising a structure that transitions from an amorphous silicon region adjacent to the first surface, to a polysilicon region adjacent to the second surface;

a second layer adjacent to the first surface of the first layer; and

a third layer adjacent to the second surface of the first layer;

wherein

at least one of the second and third layers comprises a dielectric.

2. A multi-layer assembly comprising:

a first silicon layer comprising at least first and second surfaces, and further comprising a structure having a first region composed of amorphous silicon adjacent to the first surface, a second region composed of polysilicon adjacent to the second surface, and an intermediate region between the first and second regions, the intermediate region comprised partially of amorphous silicon and partially of polysilicon;

a second layer adjacent to the first surface of the first layer; and

a third layer adjacent to the second surface of the first layer;

wherein

at least one of the second and third layers comprises a dielectric.

3. A multi-layer assembly as in claim 2, wherein the intermediate region has a continuous phase distribution from amorphous silicon to polysilicon.

4. A semiconductor device having a floating gate, the floating gate comprising a silicon structure having at least first and second surfaces and transitioning from an amorphous silicon region adjacent to the first surface to a polysilicon region adjacent to the second surface.

5. A semiconductor device having a floating gate, the floating gate comprising a silicon structure having at least first and second surfaces;

the structure comprising at least first and second regions;

the first region comprising amorphous silicon, and adjacent to the first surface; and

the second region comprising polysilicon, and adjacent to the second surface.

6. A semiconductor device as in claim 5, wherein the silicon structure further comprises an intermediate region between the first and second surfaces, wherein the intermediate region has a phase distribution that transitions from amorphous silicon to polysilicon.

8. A method as in claim 6, wherein:

the starting temperature is approximately 620°

C.; and

the ending temperature is in a range from about 500°

C. to about 550°

C.

7. A method of forming a layer on a substrate, comprising:

depositing a silicon layer on the substrate; and

controlling the temperature during the step of depositing the silicon layer, from a starting temperature favoring the formation of polysilicon, to an ending temperature favoring the formation of amorphous silicon.

9. A method of forming a floating gate on a semiconductor substrate, comprising:

forming a first dielectric layer on the semiconductor substrate;

depositing a silicon layer superposing the first layer;

forming a second dielectric layer superposing the silicon layer; and

controlling the temperature during the step of depositing the silicon layer, from a starting temperature to an ending temperature, wherein the starting temperature is higher than the ending temperature.

10. A method as in claim 9, wherein:

the starting temperature is selected to form a polysilicon region adjacent to the first dielectric layer; and

the ending temperature is selected to form an amorphous silicon region adjacent to the second dielectric layer.

11. A method as in claim 10, wherein:

the starting temperature is approximately 620°

C.; and

the ending temperature is in a range from about 500°

C. to about 550°

C.