Semiconductor device

• US 20050012153A1
• Filed: 07/12/2004
• Published: 01/20/2005
• Est. Priority Date: 07/15/2003
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Ipposhi, Takashi
• Granted Patent: US 7,183,624 B2
• Time in Patent Office: Days
• US Class Current: 257/347
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A transistor region is a region where a plurality of MOS transistors, including an MOS transistor, are formed, and a dummy region is a region lying under a spiral inductor. In the dummy region, a plurality of dummy active layers are disposed in the main surface of an SOI substrate and a plurality of dummy gate electrodes are disposed covering the respective dummy active layers. The arrangement pattern of the dummy active layers and the arrangement pattern of the dummy gate electrodes nearly match, so that the dummy gate electrodes are aligned accurately on the dummy active layers.

Claims

1. A semiconductor device comprising:

an SOI substrate having a substrate portion as a foundation, a buried oxide film provided on said substrate portion, and an SOI layer provided on said buried oxide film;

an inductance element provided above said SOI layer;

an MOS transistor provided on said SOI substrate;

a plurality of dummy active layers provided in a main surface of said SOI layer in a dummy region under said inductance element, said plurality of dummy active layers being independent of each other; and

a plurality of dummy gate electrodes provided on said main surface of said SOI layer in said dummy region and being independent of each other.

2. The semiconductor device according to claim 1, wherein an arrangement pattern of said plurality of dummy gate electrodes nearly matches with an arrangement pattern of said plurality of dummy active layers and said plurality of dummy gate electrodes are aligned on said plurality of dummy active layers.

3. The semiconductor device according to claim 1, wherein said plurality of dummy active layers are formed of portions of said SOI layer that are separated and electrically isolated from each other by an isolation insulating film that extends from the surface of said SOI layer to reach said buried oxide film through said SOI layer.

4. The semiconductor device according to claim 1, wherein, during manufacture, said plurality of dummy gate electrodes are protected from introduction of impurities into said MOS transistor.

5. The semiconductor device according to claim 4, wherein surfaces of said plurality of dummy gate electrodes are protected from silicide film formation on at least one of a gate electrode and a source/drain layer of said MOS transistor.

6. The semiconductor device according to claim 1, wherein, during manufacture, said plurality of dummy active layers are protected from introduction of impurities into said MOS transistor.

7. The semiconductor device according to claim 6, wherein surfaces of said plurality of dummy active layers are protected from silicide film formation on at least one of a gate electrode and a source/drain layer of said MOS transistor.