Semiconductor device

• US 20050012165A1
• Filed: 02/26/2004
• Published: 01/20/2005
• Est. Priority Date: 07/16/2003
• Status: Active Grant

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Otani, Hiroshi
• Granted Patent: US 6,924,537 B2
• Time in Patent Office: Days
• US Class Current: 257/414
• CPC Class Codes: B81B 7/007 Interconnections between the MEMS and external electrical signals
• CPC Class Codes: G01P 1/023 for acceleration measuring devices
• CPC Class Codes: G01P 15/0802 Details
• CPC Class Codes: G01P 15/125 by capacitive pick-up
• CPC Class Codes: G01P 2015/0814 for translational movement of the mass, e.g. shuttle type
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05 of an individual bonding area
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/2612 Auxiliary members for layer connectors, e.g. spacers
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/83805 involving forming a eutectic alloy at the bonding interface
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 23/60 Protection against electrostatic charges or discharges, e.g. Faraday shields
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/0102 : Calcium [Ca]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01068 : Erbium [Er]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/0132 : Binary Alloys
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10161 : with a rectangular active surface
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1433 : Application-specific integrated circuit [ASIC]
• CPC Class Codes: H01L 2924/1532 : the connection portion being formed on the die mounting surface of the substrate
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19107 : off-chip wires
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

A first semiconductor substrate (3) is so formed as to surround a periphery of a region between an upper substrate (1) and a lower substrate (11) like an outer peripheral frame, a potential drawing portion (31) of the first semiconductor substrate (3) is formed at a corner portion thereof and an area of the corner portion of the first semiconductor substrate (3) including the potential drawing portion (31) is made equal to or less than an area of each of potential drawing portions (36a, 36b, 40) of other semiconductor substrates (5, 7, 9), to achieve reduction in chip size. A conductive layer is formed on a surface of the upper substrate (1) or the like and the conductive layer is fixed to a fixed voltage such as a ground potential. This conductive layer or the like shields the semiconductor substrates against disturbance such as proximity of other substances, static electricity or radio wave hindrance.

Claims

1. A semiconductor device, comprising:

an upper substrate on which a plurality of through holes are formed;

a lower substrate; and

a plurality of semiconductor substrates provided between said upper substrate and said lower substrate, said plurality of semiconductor substrates forming a fixed electrode and a variable electrode, and each having a potential drawing portion, abutting on said through holes to draw potentials,

wherein one of said plurality of semiconductor substrates is so formed as to surround a periphery of a region between said upper substrate and said lower substrate, like an outer peripheral frame,

the others of said plurality of semiconductor substrates are disposed, being surrounded by an inner periphery of said outer peripheral frame formed by said one semiconductor substrate, and

said potential drawing portion of said one semiconductor substrate is formed at a corner portion thereof and an area of said corner portion of said one semiconductor substrate including said potential drawing portion is almost equal to or less than an area of each of said potential drawing portions of said other semiconductor substrates.

2. The semiconductor device according to claim 1, further comprising

a plurality of bonding pad portions formed on a surface of said upper substrate to draw to bonding wires potentials drawn from said potential drawing portions of said semiconductor substrates to said upper substrate through said through holes.

3. The semiconductor device according to claim 1, wherein

said potential drawing portions are disposed on an end portion.

4. The semiconductor device according to claim 1, wherein

a conductive layer is formed on a surface of said upper substrate, being fixed to a predetermined fixed voltage to shield said semiconductor substrates against disturbance such as proximity of other substances, static electricity or radio wave hindrance.

5. The semiconductor device according to claim 1, wherein

said one semiconductor substrate is fixed to a predetermined fixed potential.

6. The semiconductor device according to claim 4, wherein

said one semiconductor substrate is fixed to a predetermined fixed potential, and

said conductive layer is connected to said one semiconductor substrate to be fixed to said fixed potential.

7. The semiconductor device according to claim 1, wherein

a back surface of said lower substrate is die-bonded onto a conductive die pad with a predetermined conductive member interposed therebetween.

8. The semiconductor device according to claim 1, wherein

a signal processing semiconductor element is mounted on a surface of said upper substrate, and

a substrate of said semiconductor element joined onto said surface of said upper substrate is fixed to a predetermined fixed potential.

9. The semiconductor device according to claim 2, further comprising:

interconnection layers wired on said surface of said upper substrate to interconnect said through holes and said bonding pad portions, respectively;

an insulating film covering said surface of said upper substrate on which said interconnection layers are wired; and

a conductive layer formed in an upper side of said insulating film, being fixed to a predetermined fixed potential to shield said semiconductor substrates and said interconnection layers against disturbance such as proximity of other substances, static electricity or radio wave hindrance.