Reconnectable chip interface and chip package

• US 20050012191A1
• Filed: 05/25/2004
• Published: 01/20/2005
• Est. Priority Date: 07/17/2003
• Status: Abandoned Application

• Current Assignee: Alent, Inc. (Element Solutions Inc)
• Original Assignee: Alent, Inc. (Element Solutions Inc)
• Inventors: Gilleo, Kenneth B.
• Application Number:
  US10/853,696
• Publication Number:
  US 20050012191A1
• Time in Patent Office: Days
• US Class Current: 257/678
• CPC Class Codes: B81C 3/002 Aligning microparts
• CPC Class Codes: H01L 2224/05009 Bonding area integrally formed with a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/051 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/056 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/10135 Alignment aids
• CPC Class Codes: H01L 2224/16105 the bump connector connecting bonding areas being not aligned with respect to each other
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/81136 involving guiding structures, e.g. spacers or supporting members
• CPC Class Codes: H01L 2224/81139 Guiding structures on the body
• CPC Class Codes: H01L 2224/81141 Guiding structures both on and outside the body
• CPC Class Codes: H01L 2224/81193 wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81194 Lateral distribution of the bump connectors
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 2224/81898 Press-fitting, i.e. pushing the parts together and fastening by friction, e.g. by compression of one part against the other
• CPC Class Codes: H01L 23/49811 Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/81 using a bump connector
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01042 : Molybdenum [Mo]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/16152 : Cap comprising a cavity for hosting the device, e.g. U-shaped cap
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/351 : Thermal stress
• CPC Class Codes: H01L 31/0203 : Containers; Encapsulations , e.g. encapsulation of photodiodesfor photovoltaic devices H01L31/048; for organic photosensitive devices H10K30/80

Abstract

An assembly of the present invention has a substrate and an integrated circuit device adapted to be electrically and mechanically connected to the substrate. Electrical connection pads on the circuit device and on the substrate contact one another when the circuit device and the substrate are connected. At least one first projection on one of the device and on the substrate and at least two second projections on the other of the device and the substrate each have a respective axial length and are sized and shaped for a close friction fit along their axial lengths when the projections are interdigitated relative to one another. An integrated circuit device package of the present invention includes an integrated circuit device and an interconnect substrate for mounting the circuit device on an electronic circuit substrate. The interconnect substrate mates with the active side of the circuit device to form an enclosed space.

Claims

1. A integrated circuit device package comprising:

an integrated circuit device having an active side with at least one electrical connection pad thereon;

an interconnect substrate for mounting said integrated circuit device on an electronic circuit substrate, said interconnect substrate having a first side adapted to mate with the active side of the integrated circuit device to form an enclosed space and a second side adapted for electrical and mechanical connection to the electronic circuit substrate,

the interconnect substrate having at least one set of electrical connection pads, each set comprising a first electrical connection pad on the first side of the interconnect substrate adapted for electrical connection to the at least one electrical connection pad on the integrated circuit device and a second electrical connection pad on the second side of the interconnect substrate electrically connected to the first connection pad, said second electrical connection pad on the second side of the interconnect substrate being adapted for electrical and mechanical connection to the electronic circuit substrate.

2. A package as set forth in claim 1 wherein said second electrical connection pad on the interconnect substrate comprises at least one electrical conductive connecting element for connection to the electronic circuit substrate.

3. A package as set forth in claim 2 wherein said at least one electrical conductive connecting element comprises a solder ball for electrical and mechanical connection to the electronic circuit substrate.

4. A package as set forth in claim 2 wherein said at least one electrical conductive connecting element comprise a projection extending from an external surface of the second electrical connection pad.

5. A package as set forth in claim 4 wherein said projection comprises a solid cylindrical body.

6. A package as set forth in claim 4 wherein said projection is substantially rigid.

7. A package as set forth in claim 5 wherein said body is formed integral with said interconnect substrate.

8. A package as set forth in claim 2 further comprising at least two electrical conductive connecting elements on the electronic circuit substrate adapted to mate with said at least one electrical conductive connecting element on the interconnect substrate.

9. A package as set forth in claim 8 wherein said electrical conductive connecting elements on the electronic circuit substrate and on the interconnect substrate are sized and shaped for a close interdigitated friction fit relative to one another thereby to establish an electrical and mechanical connection between the package and the electronic circuit substrate.

10. A package as set forth in claim 1 wherein said interconnect substrate comprises an electrically conductive via that electrically connects said first and second electrical connection pads on the interconnect substrate.

11. A package as set forth in claim 1 wherein said first electrical connection pad on the interconnect substrate comprises at least one protrusion adapted for contact with said integrated circuit device electrical connection pad.

12. A package as set forth in claim 1 wherein said first electrical connection pad on the interconnect substrate comprises at least one spring adapted to contact the integrated circuit device electrical connection pad.

13. A package as set forth in claim 1 wherein said interconnect substrate and said integrated circuit device are approximately equal size.

14. A package as set forth in claim 1 wherein said integrated circuit device is a MEMS device.

15. A package as set forth in claim 1 wherein said interconnect substrate is translucent.

16. A package as set forth in claim 15 wherein said integrated circuit device is an optical MEMS device.

17. A package as set forth in claim 1 wherein said electronic circuit substrate is a circuit board.

18. A package as set forth in claim 1 wherein said first side of said interconnect substrate comprises an outer rim for sealing contact with said integrated circuit device.

19. A package as set forth in claim 18 wherein said first side of said interconnect substrate further comprises a recess that forms said enclosed space upon contact of said outer rim with said integrated circuit device.

20. A package as set forth in claim 19 wherein said first side of said interconnect substrate further comprises a shoulder between the recess and the outer rim for placement of the first electrical connection pad of the interconnect substrate.

21. A process for forming an integrated circuit device package, the process comprising the steps of:

fabricating an integrated circuit device wafer having an active side;

fabricating an interconnect substrate wafer such that said wafer has electrical connection pads on opposite sides thereof and a recessed surface;

electrically and mechanically connecting the integrated circuit device wafer and interconnect substrate wafer such that the two wafers form an enclosed space between the active side of said integrated circuit device wafer and the recessed surface of the interconnect substrate wafer; and

dicing the integrated circuit device wafer and interconnect substrate wafer to form one or more individual integrated circuit device packages.

22. The process as set forth in claim 21 wherein said fabricating an interconnect substrate wafer step includes configuring the interconnect substrate wafer to have at least one electrical conductive connecting element for electrical and mechanical connection to an electronic circuit substrate.

23. The process as set forth in claim 21 wherein said dicing step comprises cutting the joined wafers into said one or more individual integrated circuit device packages.

24. An interconnect substrate for mounting an integrated circuit device on an electronic circuit substrate, said interconnect substrate comprising:

a first side adapted to mate with an active side of the integrated circuit device to form an enclosed space and a second side adapted for electrical and mechanical connection to the electronic substrate,

a first electrical connection pad on the first side of the interconnect substrate adapted for electrical connection to the integrated circuit device, and

a second electrical connection pad on the second side of the interconnect substrate electrically connected to the first connection pad, said second electrical connection pad on the second side of the interconnect substrate being adapted for electrical and mechanical connection to the electronic circuit substrate.

25. An interconnect substrate as set forth in claim 24 wherein said first side of said interconnect substrate comprises an outer rim for sealing contact with said integrated circuit device.

26. An interconnect substrate as set forth in claim 25 wherein said first side of said interconnect substrate further comprises a recess that forms said enclosed space upon contact of said outer rim with said integrated circuit device.

27. An interconnect substrate as set forth in claim 25 wherein said first side of said interconnect substrate further comprises a shoulder between the recess and the outer rim for placement of the first electrical connection pad.

28. An interconnect substrate as set forth in claim 24 further comprising an electrically conductive via that electrically connects said first and second electrical connection pad.

29. An interconnect substrate as set forth in claim 24 wherein said first electrical connection pad comprises at least one protrusion adapted for contact with an electrical connection pad on the integrated circuit device.

30. An interconnect substrate as set forth in claim 24 wherein said first electrical connection pad comprises at least one spring adapted for contact with an electrical connection pad on the integrated circuit device.