Hybrid integrated circuit
First Claim
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1. A hybrid integrated circuit comprising:
- a first wiring substrate comprising a plurality of signal line layers and a plurality of ground conductive layers, each of the signal line layers and a corresponding one of the ground conductive layers making up a microstrip line;
a cavity formed in the first wiring substrate to expose one of the ground conductive layers at a bottom of the cavity;
a semiconductor chip mounted in the cavity and having a bottom surface fixed to the one of the ground conductive layers; and
a mounting component mounted to an upper surface of the first wiring substrate but not above the cavity.
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Abstract
The hybrid integrated circuit includes a first wiring substrate having a plurality of signal line layers and a plurality of ground conductive layers, each of the signal line layers and a corresponding one of the ground conductive layers making up a microstrip line; a cavity formed in the first wiring substrate to expose one of the ground conductive layers at a bottom of the cavity; a semiconductor chip mounted in the cavity and having a bottom surface fixed to the one of the ground conductive layers; and a mounting component mounted to an upper surface of the first wiring substrate but not above the cavity.
22 Citations
12 Claims
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1. A hybrid integrated circuit comprising:
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a first wiring substrate comprising a plurality of signal line layers and a plurality of ground conductive layers, each of the signal line layers and a corresponding one of the ground conductive layers making up a microstrip line;
a cavity formed in the first wiring substrate to expose one of the ground conductive layers at a bottom of the cavity;
a semiconductor chip mounted in the cavity and having a bottom surface fixed to the one of the ground conductive layers; and
a mounting component mounted to an upper surface of the first wiring substrate but not above the cavity. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A hybrid integrated circuit, comprising:
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a first wiring substrate comprising a plurality of dielectric layers;
a cavity formed in a part of a single or a plurality of the plurality of dielectric layers in an upper surface side of the first wiring substrate;
a semiconductor chip fixed to a bottom surface of the cavity; and
a second wiring substrate covering the cavity. - View Dependent Claims (11, 12)
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Specification