Multilayer wiring board and manufacture method thereof

• US 20050012217A1
• Filed: 12/10/2003
• Published: 01/20/2005
• Est. Priority Date: 12/11/2002
• Status: Active Grant

• Current Assignee: Dai Nippon Printing Company Limited
• Original Assignee: Dai Nippon Printing Company Limited
• Inventors: Nakamura, Kazunori, Kuramochi, Satoru, Akazawa, Miyuki, Nakayama, Koichi, Mori, Toshiaki
• Granted Patent: US 7,091,589 B2
• Time in Patent Office: Days
• US Class Current: 257/758
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H05K 1/0306 Inorganic insulating substrates, e.g. ceramic, glass
• CPC Class Codes: H05K 1/0366 reinforced, e.g. by fibres, fabrics H05K1/036 takes precedence
• CPC Class Codes: H05K 1/162 incorporating printed capacitors
• CPC Class Codes: H05K 2201/0195 Dielectric or adhesive layers comprising a plurality of layers, e.g. in a multilayer structure
• CPC Class Codes: H05K 2201/068 wherein the coefficient of thermal expansion is important
• CPC Class Codes: H05K 2201/09563 Metal filled via plated through-hole filled with insulating material H05K2201/0959
• CPC Class Codes: H05K 2201/09581 Applying an insulating coating on the walls of holes
• CPC Class Codes: H05K 2201/09763 Printed component having superposed conductors, but integrated in one circuit layer
• CPC Class Codes: H05K 2201/09827 Tapered, e.g. tapered hole, via or groove bevelled, chamferred or tapered edge H05K2201/09154
• CPC Class Codes: H05K 2203/025 Abrading, e.g. grinding or sand blasting deburring, rounding, bevelling or smoothing conductor edges H05K2203/0346
• CPC Class Codes: H05K 2203/1338 Chemical vapour deposition
• CPC Class Codes: H05K 2203/1581 Treating the backside of the PCB, e.g. for heating during soldering or providing a liquid coating on the backside
• CPC Class Codes: H05K 3/0041 by plasma etching
• CPC Class Codes: H05K 3/0044 Mechanical working of the substrate, e.g. drilling or punching H05K3/0008 takes precedence
• CPC Class Codes: H05K 3/388 : by the use of a metallic or inorganic thin film adhesion layer
• CPC Class Codes: H05K 3/4061 : for via connections in inorganic insulating substrates
• CPC Class Codes: H05K 3/4069 : for via connections in organic insulating substrates
• CPC Class Codes: H05K 3/4076 : by thin-film techniques
• CPC Class Codes: H05K 3/426 : initial plating of through-holes in substrates without metal
• CPC Class Codes: H05K 3/4605 : made from inorganic insulating material
• CPC Class Codes: Y10T 29/43 : Electric condenser making
• CPC Class Codes: Y10T 29/49117 : Conductor or circuit manufacturing
• CPC Class Codes: Y10T 29/49124 : On flat or curved insulated base, e.g., printed circuit, etc.
• CPC Class Codes: Y10T 29/49126 : Assembling bases
• CPC Class Codes: Y10T 29/49153 : with shaping or forcing terminal into base aperture
• CPC Class Codes: Y10T 29/49155 : Manufacturing circuit on or in base
• CPC Class Codes: Y10T 29/49165 : by forming conductive walled aperture in base

Abstract

In a multilayer wiring board comprising a core board, and a wiring layer and an electrically insulating layer that are stacked on one surface of said core board, a thermal expansion coefficient of said core board in XY directions falls within a range of 2 to 20 ppm, a core member for said core board is a core member selected from silicon, ceramics, glass, a glass-epoxy composite, and metal, said core board is provided with a plurality of through holes that are made conductive between the front and the back by a conductive material, and a capacitor is provided on one surface of said core board, wherein said capacitor comprises an upper electrode being the conductive material in said through hole, and a lower electrode disposed so as to confront said upper electrode via a dielectric layer.

Claims

1. A multilayer wiring board comprising a core board, and a wiring layer and an electrically insulating layer that are stacked on one surface or both surfaces of said core board, characterized by having a structure, wherein

a thermal expansion coefficient, in XY directions, of a core member used for said core board falls within a range of 2 to 20 ppm, and said core member is a core member selected from silicon, ceramics, glass, and a glass-epoxy composite,

said core board has its front and back that are electrically connected by a plurality of through holes filled with a conductive material, and

said conductive material protrudes from a surface of said core member at least on one side thereof.

2. A multilayer wiring board according to claim 1, wherein a thickness of said core member falls within a range of 50 to 500 μ

m, an opening diameter of said through hole on the front side, being a semiconductor chip mounting side, of said core member falls within a range of 10 to 200 μ

m, an opening diameter of said through hole on the back side of said core member falls within a range of 10 to 175 μ

m, the opening diameter on the back side is equal to or less than the opening diameter on the front side, and said conductive material protrudes from the surface of said core member within a range of 5 to 15 μ

m.

3. A multilayer wiring board according to claim 1, wherein said conductive material protrudes from the surface of said core member within a range of 5 to 15 μ

m to form a land, and a diameter of said land is larger than an opening diameter of said through hole filled with said conductive material.

4. A multilayer wiring board according to claim 3, wherein peripheral portions around said protruding lands are covered with an electrically insulating layer so that a flat surface is formed.

5. A multilayer wiring board according to claim 1, wherein an insulating layer is provided on inner wall surfaces of said through holes of said core member and on the surface of said core member.

6. A multilayer wiring board according to claim 1, wherein an opening diameter of said through hole of said core member falls within a range of 10 to 100 μ

m, and a conductive substance diffusion preventing layer is provided on inner wall surfaces of said through holes.

7. A multilayer wiring board according to claim 6, wherein said conductive substance diffusion preventing layer is a thin film of titanium nitride.

8. A multilayer wiring board according to claim 6, wherein an opening diameter of said through hole of said core member falls within a range of 10 to 30 μ

m.

9. A manufacture method of a multilayer wiring board comprising a core board, and a wiring layer and an electrically insulating layer that are stacked on one surface or both surfaces of said core board, said manufacture method characterized by comprising:

a step of forming through holes in a core member used for said core board, said core member having a thermal expansion coefficient in XY directions that falls within a range of 2 to 20 ppm, and selected from silicon, ceramics, glass, and a glass-epoxy composite;

a step of masking both surfaces of said core member other than said through holes and land forming regions using resists;

a step of filling a conductive material into said through holes and said land forming regions, then polishing both surfaces of said core member, and then peeling off said resists to form said core board;

a step of forming an electrically insulating layer at predetermined portions of said core board; and

forming wiring layers on one surface or both surfaces of said core board via said electrically insulating layer.

10. A manufacture method of a multilayer wiring board according to claim 9, wherein a method of filling the conductive material is either of a method in which a conductive film is formed in said through holes from one surface of said core member by a vacuum film forming method so as to serve as a seed layer and, using said seed layer, metal is deposited and filled in said through holes by electrolytic plating, or a method in which a conductive substance diffusion preventing layer is formed in said through holes by an MO-CVD method, then a conductive film is formed in said through holes from one surface of said core member by a vacuum film forming method so as to serve as a seed layer and, using said seed layer, metal is deposited and filled in said through holes by electrolytic plating.

11. A manufacture method of a multilayer wiring board according to claim 9, wherein a method of filling the conductive material fills conductive paste.

12. A manufacture method of a multilayer wiring board according to claim 9, wherein, after forming the through holes, a conductive substance diffusion preventing layer is formed on inner wall surfaces of said through holes.

13. A manufacture method of a multilayer wiring board according to claim 12, wherein a forming method of said conductive substance diffusion preventing layer is an MO-CVD method.

14. A manufacture method of a multilayer wiring board according to claim 9, wherein a forming method of said through holes is an ICP-RIE method or a sandblasting method.

15. A manufacture method of a multilayer wiring board according to claim 9, wherein a forming method of said through holes uses an ICP-RIE method on the side where an opening diameter of said through hole is small, and uses a sandblasting method on the side where the opening diameter is large.

16. A manufacture method of a multilayer wiring board according to claim 9, wherein the forming step of said through holes forms fine holes in the core member, then polishes the core member to form penetrating holes.

17. A manufacture method of a multilayer wiring board according to claim 9, wherein the forming step of said through holes polishes the core member to a desired thickness, then grinds the core member from one surface or both surfaces thereof by a sandblasting method to form penetrating holes.

18. A manufacture method of a multilayer wiring board comprising a core board, and a wiring layer and an electrically insulating layer that are stacked on one surface or both surfaces of said core board, said manufacture method characterized by comprising:

a step of forming insulating layers on both surfaces of a core member other than through hole forming regions, said core member used for said core board, having a thermal expansion coefficient in XY directions that falls within a range of 2 to 20 ppm, and selected from silicon, ceramics, glass, and a glass-epoxy composite;

a step of masking said insulating layers using resists;

a step of applying sandblasting to the core member using said resists as masks, to thereby form through holes in the core member;

a step of filling a conductive material into said through hole, peeling off said resists, then polishing both sides of the core member to form the core board; and

a step of forming a wiring layer on one surface or both surfaces of said core board via an electrically insulating layer.

19. A manufacture method of a multilayer wiring board according to claim 18, wherein a method of filling the conductive material into the through holes forms an under conductive thin film in the through holes from one surface of the core member by a vacuum film forming method so as to serve as a seed layer and, using said seed layer, deposits and fills metal in the through holes by electrolytic plating.

20. A manufacture method of a multilayer wiring board according to claim 18, wherein a method of filling the conductive material into the through holes fills conductive paste.

21. A manufacture method of a multilayer wiring board according to claim 18, wherein, after forming the through holes, a conductive substance diffusion preventing layer is formed on inner wall surfaces of said through holes.

22. A manufacture method of a multilayer wiring board according to claim 21, wherein a forming method of said conductive substance diffusion preventing layer is an MO-CVD method.

23. A manufacture method of a multilayer wiring board according to claim 18, wherein a forming method of said insulating layers is an insulating layer forming method based on thermal oxidation of the core member, or an insulating layer forming method using a CVD method.

24. A multilayer wiring board comprising a core board, and a wiring layer and an electrically insulating layer that are stacked on said core board, characterized in that

a thermal expansion coefficient of said core board in XY directions falls within a range of 2 to 20 ppm, and a core member for said core board is a core member selected from silicon, ceramics, glass, a glass-epoxy composite, and metal,

said core board is provided with a plurality of through holes that are made conductive between the front and the back by a conductive material, and

a capacitor is provided on one surface of said core board.

25. A multilayer wiring board according to claim 24, wherein said capacitor comprises an upper electrode being the conductive material in said through hole, and a lower electrode disposed so as to confront said upper electrode via a dielectric layer.

26. A multilayer wiring board according to claim 24, wherein said capacitor comprises an upper electrode provided on said core board so as to be connected to the conductive material in said through hole, and a lower electrode disposed so as to confront said upper electrode via a dielectric layer.

27. A multilayer wiring board according to claim 24, wherein said capacitor comprises an upper electrode provided on said core board via an electrically insulating layer so as to be connected to the conductive material in said through hole, a dielectric layer provided so as to cover at least part of said upper electrode, and a lower electrode provided so as to cover at least part of said dielectric layer.

28. A multilayer wiring board according to claim 24, wherein said capacitor comprises an upper electrode made of anodizable metal and provided on said core board so as to connected to the conductive material in said through hole, and a lower electrode disposed so as to confront said upper electrode via a dielectric layer made of an oxide of said metal.

29. A multilayer wiring board according to claim 24, wherein a material of a dielectric layer forming said capacitor is one selected from silicon oxide, silicon nitride, barium strontium titanate, tantalum pentoxide, lead zirconate titanate, strontium titanate, aluminum oxide, benzocyclobutene resin, cardo resin, and polyimide resin.

30. A multilayer wiring board according to claim 24, wherein a material of said wiring layer and said lower electrode is selected from the group consisting of one kind of metal among Al, Cr, Cu, Ti, Pt, Ru, Ta, and W, and an oxide, a nitride, or an alloy of said metal, and a multilayer film in optional combination of said metal, said oxide, said nitride, said alloy, and polysilicon.

31. A multilayer wiring board according to claim 24, wherein a thickness of said core board falls within a range of 50 to 300 μ

m, and an opening diameter of said through hole falls within a range of 10 to 300 μ

m.

32. A multilayer wiring board according to claim 24, wherein a conductive substance diffusion preventing layer is provided on inner wall surfaces of said through holes.

33. A multilayer wiring board according to claim 32, wherein said conductive substance diffusion preventing layer is a thin film of titanium nitride.

34. A multilayer wiring board according to claim 32, wherein an opening diameter of said through hole of said core member falls within a range of 10 to 30 μ

m.

35. A manufacture method of a multilayer wiring board comprising a core board, and a wiring layer and an electrically insulating layer that are stacked on said core board, said manufacture method characterized by comprising:

a step of forming a plurality of fine holes in a core member, wherein a thermal expansion coefficient of said core board in XY directions falls within a range of 2 to 20 ppm, and said core member is selected from silicon, ceramics, glass, a glass-epoxy composite, and metal;

a step of causing said fine holes to be conductive by a conductive material;

a step of stacking a wiring layer and an electrically insulating layer on the core board on the fine hole perforation side to form a multilayer wiring layer;

a step of polishing a surface of the core board other than a surface where said fine holes are formed, and exposing said fine holes caused to be conductive by said conductive material, thereby to form a plurality of through holes electrically connecting between the front and the back of the core board; and

a step of forming a capacitor on said polished surface of the core board.

36. A manufacture method of a multilayer wiring board according to claim 35, wherein the step of forming the capacitor forms a dielectric layer on the surface of the core board, forms an opening in the dielectric layer on the predetermined through hole to provide a wiring layer, uses, as an upper electrode, the conductive material in the through hole where the dielectric layer has no opening, and provides a lower electrode via said dielectric layer on said through hole, thereby to form the capacitor.

37. A manufacture method of a multilayer wiring board according to claim 35, wherein the step of forming the capacitor comprises:

a step of forming an upper electrode on the surface of said core board so as to be connected to the conductive material in the through hole located at a position where the capacitor is formed;

a step of forming a dielectric layer on the surface of the core board so as to cover said upper electrode; and

a step of forming an opening in the dielectric layer on the through hole located at a position where the capacitor is not formed, to provide a wiring layer, and providing a lower electrode so as to confront said upper electrode via the dielectric layer.

38. A manufacture method of a multilayer wiring board according to claim 35, wherein the step of forming the capacitor comprises:

a step of forming an electrically insulating layer on the surface of the core board, forming an upper electrode on said electrically insulating layer so as to be connected to the conductive material in the through hole located at a position where the capacitor is formed, and forming a wiring layer so as to be connected to the conductive material in the through hole located at a position where the capacitor is not formed; and

a step of forming a dielectric layer on said electrically insulating layer so as to cover at least part of said upper electrode, and forming a lower electrode so as to cover at least part of said dielectric layer.

39. A manufacture method of a multilayer wiring board according to claim 35, wherein the step of forming the capacitor comprises:

a step of forming an upper electrode made of anodizable metal on the surface of said core board;

a step of anodizing the surface of said upper electrode to metal oxide, thereby to form a dielectric layer;

a step of forming a lower electrode on said dielectric layer; and

a step of forming a wiring layer so as to connect between the conductive material in the through hole located at a position where the capacitor is formed, and said upper electrode, and forming a wiring layer on the through hole located at a position where the capacitor is not formed.

40. A manufacture method of a multilayer wiring board according to claim 35, wherein, after forming the fine holes of which an opening diameter falls within a range of 10 to 300 μ

m, a conductive substance diffusion preventing layer is formed on inner wall surfaces of said fine holes.

41. A manufacture method of a multilayer wiring board according to claim 40, wherein a forming method of said conductive substance diffusion preventing layer is an MO-CVD method.

42. A manufacture method of a multilayer wiring board according to claim 40, wherein said fine holes are formed so that an opening diameter thereof falls within a range of 10 to 30 μ

m.

43. A manufacture method of a multilayer wiring board according to claim 35, wherein a forming method of said fine holes is an ICP-RIE method or a sandblasting method.

44. A manufacture method of a multilayer wiring board according to claim 35, wherein the step of causing the fine holes to be conductive by the conductive material is either of a method of filling conductive paste into the fine holes, and a method of filling the conductive material into the fine holes by plating.

45. A manufacture method of a multilayer wiring board according to claim 44, wherein the method of filling the conductive material by plating forms an under conductive thin film by a vacuum film forming method from the side of the core member where the fine holes are formed, forms a seed layer made of said under conductive thin film on part of inner wall surfaces of the fine holes and, using said seed layer, deposits and fills metal in the fine holes by electrolytic plating.

46. A manufacture method of a multilayer wiring board comprising a core board, and a wiring layer and an electrically insulating layer that are stacked on said core board, said manufacture method characterized by comprising:

a step of forming a plurality of through holes in a core member, wherein a thermal expansion coefficient of said core board in XY directions falls within a range of 2 to 20 ppm, and said core member is selected from silicon, ceramics, glass, a glass-epoxy composite, and metal;

a step of causing said through holes to be conductive by a conductive material thereby to electrically connect between the front and the back of the core board;

a step of stacking a wiring layer and an electrically insulating layer on one surface of said core board to form a multilayer wiring layer; and

a step of forming a capacitor on the other surface of said core board.

47. A manufacture method of a multilayer wiring board according to claim 46, wherein the step of forming the capacitor forms a dielectric layer on the surface of the core board, forms an opening in the dielectric layer on the predetermined through hole to provide a wiring layer, uses, as an upper electrode, the conductive material in the through hole where the dielectric layer has no opening, and provides a lower electrode via said dielectric layer on said through hole, thereby to form the capacitor.

48. A manufacture method of a multilayer wiring board according to claim 46, wherein the step of forming the capacitor comprises:

a step of forming an upper electrode on the surface of said core board so as to be connected to the conductive material in the through hole located at a position where the capacitor is formed;

a step of forming a dielectric layer on the surface of the core board so as to cover said upper electrode; and

a step of forming an opening in the dielectric layer on the through hole located at a position where the capacitor is not formed, to provide a wiring layer, and providing a lower electrode so as to confront said upper electrode via the dielectric layer.

49. A manufacture method of a multilayer wiring board according to claim 46, wherein the step of forming the capacitor comprises:

a step of forming an electrically insulating layer on the surface of the core board, forming an upper electrode on said electrically insulating layer so as to be connected to the conductive material in the through hole located at a position where the capacitor is formed, and forming a wiring layer so as to be connected to the conductive material in the through hole located at a position where the capacitor is not formed; and

a step of forming a dielectric layer on said electrically insulating layer so as to cover at least part of said upper electrode, and forming a lower electrode so as to cover at least part of said dielectric layer.

50. A manufacture method of a multilayer wiring board according to claim 46, wherein the step of forming the capacitor comprises:

a step of forming an upper electrode made of anodizable metal on the surface of said core board;

a step of anodizing the surface of said upper electrode to metal oxide, thereby to form a dielectric layer;

a step of forming a lower electrode on said dielectric layer; and

a step of forming a wiring layer so as to connect between the conductive material in the through hole located at a position where the capacitor is formed, and said upper electrode, and forming a wiring layer on the through hole located at a position where the capacitor is not formed.

51. A manufacture method of a multilayer wiring board according to claim 46, wherein the step of causing said through holes to be conductive by a conductive material thereby to electrically connect between the front and the back of the core board comprises:

a step of forming an under conductive thin film from one surface of the core board by a vacuum film forming method to form a seed layer made of said under conductive thin film on part of inner wall surfaces of the through holes; and

a step of depositing/growing metal in the through holes from said seed layer by electrolytic plating using said seed layer as a power feed layer.

52. A manufacture method of a multilayer wiring board according to claim 46, wherein, after forming the through holes, a conductive substance diffusion preventing layer is formed on inner wall surfaces of said through holes.

53. A manufacture method of a multilayer wiring board according to claim 52, wherein a forming method of said conductive substance diffusion preventing layer is an MO-CVD method.

54. A manufacture method of a multilayer wiring board according to claim 52, wherein said through holes are formed so that an opening diameter thereof falls within a range of 10 to 30 μ

m.

55. A manufacture method of a multilayer wiring board according to claim 46, wherein a forming method of said through holes is an ICP-RIE method or a sandblasting method.