Method and apparatus for determining characteristics of MOS devices

• US 20050012556A1
• Filed: 07/18/2003
• Published: 01/20/2005
• Est. Priority Date: 07/18/2003
• Status: Active Grant

• Current Assignee: X Corp. (f/k/a Twitter, Inc.) (X Holdings Corp.)
• Original Assignee: International Business Machines Corporation
• Inventors: Ketchen, Mark B., Bhushan, Manjul
• Granted Patent: US 7,069,525 B2
• Time in Patent Office: Days
• US Class Current: 331/57
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A set of ring oscillators is formed within a predetermined distance of each other. Each ring oscillator includes a number of coupled stages. The stages for a first given ring oscillator include an inverter having one or more first MOS devices having a first gate length. The stages for a second given ring oscillator include an inverter substantially identical to the inverters in the coupled stages of the first given ring oscillator and one or more second MOS devices having a second designed gate length. The stages for a third given ring oscillator comprise an inverter substantially identical to the inverters in the coupled stages of the first given ring oscillator and one or more third MOS devices having a third designed gate length. The second and third designed gate lengths are different and one of the second and third designed gate lengths is approximately equal to the first designed gate length. Performance is measured by using one of more of the given ring oscillators. The set of ring oscillators is used to determine one or more additional characteristics of MOS devices in the ring oscillators. A single test structure may be used to determine physical gate length (Lpoly), gate oxide thickness (Tox), gate capacitance (C), effective gate resistance (Rsw), gate tunneling current (Ig), channel leakage current per unit width (Ic), and active power (P).

Claims

1. A method for determining characteristics of metal oxide semiconductor (MOS) devices, the method comprising the steps of:

providing a plurality of ring oscillators, the plurality of ring oscillators located within a predetermined distance of one another, each ring oscillator comprising a plurality of coupled stages, wherein;

each of the plurality of coupled stages for a first given ring oscillator comprises an inverter having at least one first MOS device having a first designed gate length;

each of the plurality of coupled stages for a second given ring oscillator comprises an inverter substantially identical to the inverters in the coupled stages of the first given ring oscillator and coupled to at least one second MOS device having a second designed gate length;

each of the plurality of coupled stages for a third given ring oscillator comprises an inverter substantially identical to the inverters in the coupled stages of the first given ring oscillator and coupled to at least one third MOS device having a third designed gate length;

the second and third designed gate lengths are different; and

one of the second and third designed gate lengths is approximately equal to the first designed gate length;

determining performance by using at least one of the given ring oscillators; and

determining, using the plurality of ring oscillators, at least one additional characteristic of MOS devices in the plurality of ring oscillators.

2. The method of claim 1, wherein the step of determining performance further comprises the steps of causing the at least one given ring oscillator to oscillate so that a delay of a coupled stage in the at least one given ring oscillator is under 30 picoseconds.

3. The method of claim 1, wherein the predetermined distance is approximately 1,000 microns or less.

4. The method of claim 1, wherein the plurality of ring oscillators are coupled together through circuitry.

5. The method of claim 1, wherein the at least one second MOS device comprises an NMOS gate and a PMOS gate coupled together in parallel, and wherein the at least one third MOS device comprises an NMOS gate and a PMOS gate coupled together in parallel.

6. The method of claim 1, wherein the plurality of ring oscillators comprise five ring oscillators, wherein the at least one second MOS device comprises at least one NMOS gate, wherein the at least one third MOS device comprises at least one NMOS gate, wherein each of the plurality of coupled stages for a fourth given ring oscillator comprises an inverter coupled to at least one first PMOS gate having a fourth designed gate length, and wherein each of the plurality of stages for a fifth given ring oscillator comprises an inverter coupled to at least one second PMOS gate having a fifth designed gate length, wherein the fourth and fifth designed gate lengths are different.

7. The method of claim 1, wherein the plurality of ring oscillators comprise a fourth given ring oscillator, wherein each of the plurality of stages for the fourth given ring oscillator comprises an inverter coupled to at least one fourth MOS device having a fourth designed gate length, wherein the fourth designed gate length is larger than the third designed gate length, and wherein the third designed gate length is larger than the second designed gate length.

8. The method of claim 7, wherein each of the at least one second, third and fourth MOS devices comprises at least one NMOS gate.

9. The method of claim 7, wherein each of the at least one second, third and fourth MOS devices comprises at least one PMOS gate.

10. The method of claim 1, wherein the step of determining at least one additional characteristic further comprises the steps of:

measuring a frequency of oscillation for each of at least the first, second, and third given ring oscillators of the plurality of ring oscillators;

determining delay for each of at least the first, second, and third given ring oscillators of the plurality of ring oscillators by using at least a corresponding one of the frequencies;

measuring active and quiescent current for each of at least the first, second, and third given ring oscillators of the plurality of ring oscillators;

determining load capacitance per stage for each of at least the first, second, and third given ring oscillators of the plurality of ring oscillators by using, for a respective one of the ring oscillators, at least the active and quiescent currents and delay.

11. The method of claim 10, wherein the step of determining at least one additional characteristic of MOS devices further comprises the step of determining physical gate length for a selected one of the given ring oscillators by using the designed gate length for the selected one of the ring oscillators and a bias length.

12. The method of claim 11, wherein the step of determining at least one additional characteristic of MOS devices further comprises the step of determining bias length by comparing capacitances determined for at least each of the first, second and third given ring oscillators with designed gate length for at least each of the first, second and third given ring oscillators.

13. The method of claim 11, wherein the selected one given ring oscillator is the third given ring oscillator, wherein the third designed gate length is greater than the second designed gate length, and wherein the step of determining at least one additional characteristic of MOS devices further comprises the step of determining gate tunneling current per unit area by using at least the active current for the second and the third given ring oscillators and the designed gate lengths for the second and third given ring oscillators.

14. The method of claim 10, wherein the step of determining at least one additional characteristic of MOS devices further comprises the step of determining a thickness of oxide by using at least the load capacitance per stage for the second given ring oscillator and the load capacitance per stage for the third given ring oscillator.

15. The method of claim 10, wherein the step of determining at least one additional characteristic of MOS devices further comprises the step of determining an effective gate resistance by using at least the delays and capacitances for the first given ring oscillator and another of the given ring oscillators.

16. The method of claim 12, wherein the step of determining at least one additional characteristic of MOS devices further comprises the step of determining channel leakage current per unit width by using at least the gate tunneling current, the quiescent current for the first given ring oscillator and the physical gate length for the first given ring oscillator.

17. The method of claim 10, wherein the step of determining at least one additional characteristic of MOS devices further comprises the step of determining active power by using at least the active current and quiescent current for a selected one of the ring oscillators or by using the load capacitance and delay for a selected one of the ring oscillators.

18. The method of claim 10, wherein the step of determining at least one additional characteristic of MOS devices further comprises the step of determining short circuit power at a supply voltage by using the load capacitance, the supply voltage, and the delay for a selected one of the ring oscillators.

19. An apparatus for determining characteristics of metal oxide semiconductor (MOS) devices, the apparatus comprising:

a plurality of ring oscillators, the plurality of ring oscillators located within a predetermined distance of each other, each ring oscillator comprising a plurality of coupled stages, wherein;

each of the plurality of coupled stages for a first given ring oscillator comprises an inverter having at least one first MOS device having a first designed gate length;

each of the plurality of coupled stages for a second given ring oscillator comprises an inverter substantially identical to the inverters in the coupled stages of the first given ring oscillator and coupled to at least one second MOS device having a second designed gate length;

each of the plurality of coupled stages for a third given ring oscillator comprises an inverter substantially identical to the inverters in the coupled stages of the first given ring oscillator and coupled to at least one third MOS device having a third designed gate length;

the second and third designed gate lengths are different; and

one of the second and third designed gate lengths is approximately equal to the first designed gate length.

20. The apparatus of claim 19, wherein each ring oscillator comprises a frequency divider.

21. The apparatus of claim 19, wherein the ring oscillators are coupled together through circuitry.

22. The apparatus of claim 21, wherein the circuitry comprises a frequency divider coupled to each of the ring oscillators.

25. The apparatus of claim 19, wherein the at least one second MOS device comprises an NMOS gate and a PMOS gate coupled together in parallel, and wherein the at least one third MOS device comprises an NMOS gate and a PMOS gate coupled together in parallel.

26. The apparatus of claim 19, wherein the plurality of ring oscillators comprise five ring oscillators, wherein the at least one second MOS device comprises at least one NMOS gate, wherein the at least one third MOS device comprises at least one NMOS gate, wherein each of the plurality of coupled stages for a fourth given ring oscillator comprises an inverter coupled to at least one first PMOS gate having a fourth designed gate length, wherein each of the plurality of coupled stages for a fifth given ring oscillator comprises an inverter coupled to at least one second PMOS gate having a fifth designed gate length, and wherein the fourth and fifth designed gate lengths are different.

27. The apparatus of claim 19, wherein the plurality of ring oscillators comprise a fourth given ring oscillator, wherein each of the plurality of coupled stages for the fourth given ring oscillator comprises an inverter coupled to at least one fourth MOS device having a fourth designed gate length, wherein the fourth designed gate length is greater than the third designed gate length, and wherein the third designed gate length is greater than the second designed gate length.

28. The apparatus of claim 27, wherein each of the at least one second, third and fourth MOS devices comprises at least one NMOS gate.

29. The apparatus of claim 27, wherein each of the at least one second, third and fourth MOS devices comprises at least one PMOS gate.

23. The apparatus of 19, wherein each of ring oscillators is coupled to an independent power supply, and wherein the circuitry is coupled to another independent power supply.

24. The apparatus of claim 23, wherein each independent power supply can be separately enabled.

30. A semiconductor including at least one circuit for determining characteristics of metal oxide semiconductor (MOS) devices, the at least one circuit comprising:

a plurality of ring oscillators, the plurality of ring oscillators located within a predetermined distance of each other, each ring oscillator comprising a plurality of coupled stages, wherein;

each of the plurality of coupled stages for a first given ring oscillator comprises an inverter having at least one first MOS device having a first designed gate length;

each of the plurality of coupled stages for a second given ring oscillator comprises an inverter substantially identical to the inverters in the coupled stages of the first given ring oscillator and coupled to at least one second MOS device having a second designed gate length;

each of the plurality of coupled stages for a third given ring oscillator comprises an inverter substantially identical to the inverters in the coupled stages of the first given ring oscillator and coupled to at least one third MOS device having a third designed gate length;

the second and third designed gate lengths are different; and

one of the second and third designed gate lengths is approximately equal to the first designed gate length.

31. A method for determining characteristics of metal oxide semiconductor (MOS) devices, the method comprising the steps of:

determining performance by using at least one of a plurality of ring oscillators, the plurality of ring oscillators located within a predetermined distance of one another, each ring oscillator comprising a plurality of coupled stages, wherein;

each of the plurality of coupled stages for a first given ring oscillator comprises an inverter having at least one first MOS device having a first designed gate length;

each of the plurality of coupled stages for a second given ring oscillator comprises an inverter substantially identical to the inverters in the coupled stages of the first given ring oscillator and coupled to at least one second MOS device having a second designed gate length;

each of the plurality of coupled stages for a third given ring oscillator comprises an inverter substantially identical to the inverters in the coupled stages of the first given ring oscillator and coupled to at least one third MOS device having a third designed gate length;

the second and third designed gate lengths are different; and

one of the second and third designed gate lengths is approximately equal to the first designed gate length; and

determining, using the plurality of ring oscillators, at least one additional characteristic of MOS devices in the plurality of ring oscillators.