Display device and electronic apparatus
First Claim
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1. A display device comprising:
- a plurality of gate signal lines over a substrate;
a pixel portion having a plurality of pixels over the substrate; and
a gate signal line driver circuit connected to the gate lines over the substrate, wherein the gate signal line driver circuit comprises a latch circuit for storing data of whether each gate signal line is driven, a buffer circuit for driving the gate signal lines, and a circuit for controlling the buffer circuit by the latch circuit.
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Abstract
When a pixel and a signal line driver circuit are made up of semi-amorphous TFTs, an amplitude for driving the pixel has to be made larger, and a high power supply voltage is needed. The high power supply voltage increases power consumption in the case of partial drive. According to the invention, in order to reduce power consumption, a gate signal line driver circuit stores data of whether each gate signal line is used for displaying an image or not, thereby stopping driving of a gate signal line which is not required to be driven.
38 Citations
20 Claims
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1. A display device comprising:
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a plurality of gate signal lines over a substrate;
a pixel portion having a plurality of pixels over the substrate; and
a gate signal line driver circuit connected to the gate lines over the substrate, wherein the gate signal line driver circuit comprises a latch circuit for storing data of whether each gate signal line is driven, a buffer circuit for driving the gate signal lines, and a circuit for controlling the buffer circuit by the latch circuit. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A display device comprising:
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a plurality of gate signal lines over a substrate;
a pixel portion having a plurality of pixels over the substrate; and
a gate signal line driver circuit comprising a shift register, a first switch circuit, a second switch circuit, a latch circuit, and a buffer circuit, wherein the first switch circuit is inputted with a first switching signal and an output of the shift register, and the first switch circuit outputs a signal to the latch circuit or the second switch circuit, wherein the second switch circuit is inputted with an output of the latch circuit and with the signal outputted from one of the first switch circuit and a ground potential, and the second switch circuit outputs a signal to a inverter of the buffer circuit, and wherein the latch circuit is controlled by a latch pulse and stores the output of the first switch circuit. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification
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Current AssigneeSemiconductor Energy Laboratory Co., Ltd.
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Original AssigneeSemiconductor Energy Laboratory Co., Ltd.
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InventorsFuruno, Makoto, Maekawa, Shinji, Nakamura, Osamu, Koyama, Jun, Yamazaki, Shunpei, Imai, Keitaro
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Granted Patent
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Time in Patent OfficeDays
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Field of Search
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US Class Current345/205
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CPC Class CodesG02F 1/1368 in which the switching elem...G09G 2300/0408 Integration of the drivers ...G09G 2300/0417 Special arrangements specif...G09G 2300/0426 Layout of electrodes and co...G09G 2300/0842 forming a memory circuit, e...G09G 2300/0861 with additional control of ...G09G 2310/04 Partial updating of the dis...G09G 2320/0223 Compensation for problems r...G09G 2320/043 Preventing or counteracting...G09G 2330/021 Power management, e.g. powe...G09G 3/3266 Details of drivers for scan...G09G 3/3648 using an active matrix G09G...G09G 3/3677 suitable for active matrice...
