Image input apparatus

• US 20050012826A1
• Filed: 08/20/2004
• Published: 01/20/2005
• Est. Priority Date: 04/24/1998
• Status: Active Grant

• Current Assignee: Hisataka Hirose, Yuichiro Hattori
• Original Assignee: Hisataka Hirose, Yuichiro Hattori
• Inventors: Hattori, Yuichiro, Hirose, Hisataka
• Granted Patent: US 7,499,080 B2
• Time in Patent Office: Days
• US Class Current: 348/220.100
• CPC Class Codes: H04N 25/443 by reading pixels from selected 2D regions of the array, e.g. for windowing or digital zooming
• CPC Class Codes: H04N 5/765 Interface circuits between an apparatus for recording and another apparatus
• CPC Class Codes: H04N 5/772 the recording apparatus and the television camera being placed in the same enclosure
• CPC Class Codes: H04N 9/7921 for more than one processing mode
• CPC Class Codes: H04N 9/804 involving pulse code modulation of the colour picture signal components

Abstract

This invention relates to a video camera for inputting an image of an object as an electrical signal. This video camera includes a CCD, a clock selector for selecting a clock having a frequency corresponding to a read object region in which pixels are read out from the CCD, a CCD controller for driving the CCD in accordance with the clock having the selected frequency to read out pixels from the read object region, and a monitor for displaying an image on the basis of the pixels read out from the CCD.

Claims

1. (cancelled)

2. An image input apparatus, comprising:

an image sensing device having pixels arranged in two dimensions;

a selector arranged to select a first operation mode or a second operation mode of the image sensing apparatus;

a driving circuit arranged to drive the image sensing device such that signals of first pixels included in a first region of the image sensing device are read out in the first mode and signals of second pixels included in a second region of the image sensing device are read out in the second mode, wherein the second region is larger than the first region and number of the second pixels is larger than number of the first pixels;

a signal processing circuit arranged to process signals read out from the image sensing device; and

a recording unit arranged to record signals processed by the signal processing circuit in a recording medium with a predetermined format in the first operation mode,

wherein number of pixels of the image sensing device is larger than number of pixels which is defined by the predetermined format,

the driving circuit is further arranged to drive the image sensing device such that, in the first operation mode, the signals of the first pixels are read out from the first region in a first vertical scanning period and, in the second mode, the signals of the second pixels are read out from the second region in a second vertical scanning period that is longer than the first vertical scanning period, and

the first operation mode is a mode of recording a motion image and the second mode is a mode of recording a still image.

3. The apparatus according to claim 2, wherein the predetermined format is a recording format corresponding to NTSC standard television format.

4. The apparatus according to claim 2, wherein the driving circuit is further arranged to drive the image sensing device such that the signals of the first pixels are read out from the image sensing device by decimating signals of pixels of plural lines in the image sensing device,

the signal processing circuit is further arranged to decimate signals of both sides of each of plural lines in the first region, and

the recording unit is further arranged to record the signals subjected to decimation by the signal processing circuit.

5. The apparatus according to claim 2, wherein the driving circuit is further arranged to drive the image sensing device such that the signals of the first pixels are read out from the image sensing device in non-interlace manner in the first operation mode, and the signals of the second pixels are read out from the image sensing device in non-interlace manner in the second operation mode,

the signal processing circuit is further arranged, in the first operation mode, to store the signals of the first pixels read out in non-interlace manner into a memory and to read out the signals stored in the memory such that interlaced signals are generated, and

the recording unit is further arranged to record the interlaced signals in the recording medium.