Memory circuit, display device and electronic equipment each comprising the same

• US 20050013180A1
• Filed: 07/14/2004
• Published: 01/20/2005
• Est. Priority Date: 07/18/2003
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Atsumi, Tomoaki, Koyama, Jun
• Granted Patent: US 7,675,512 B2
• Time in Patent Office: Days
• US Class Current: 365/199
• CPC Class Codes: G11C 11/4085 Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
• CPC Class Codes: G11C 11/418 Address circuits
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Abstract

A memory circuit using a thin film transistor has been problems such as the drop in yield and the decrease in speed of response of the memory circuit due to variations in transistors. The purpose of the invention is to improve the yield and speed of the response of a memory cell by driving a word line by a voltage which is different from the logical amplitude of the memory cell. The invention is applicable to an SRAM, a DRAM, a mask ROM, and the like. A memory circuit of the invention is formed integrally with a display device for realizing a multi-functional display device.

Claims

1. A memory circuit comprising:

a word line, a plurality of memory cells, and a driver circuit for driving the word line,

wherein the driver circuit for driving the word line includes a level shift circuit, and

wherein an output amplitude of me memory cell and an output amplitude of the level shift circuit are different from each other.

8. The memory circuit according to claim 1, wherein the memory circuit is a SRAM.

9. The memory circuit according to claim 1, wherein the memory circuit is a DRAM.

10. The memory circuit according to claim 1, wherein the memory circuit is a mask ROM.

11. The memory circuit according to claim 1, wherein the memory circuit comprises a thin film transistor.

12. The memory circuit according to claim 1, wherein the memory circuit is incorporated in a display device.

13. The memory circuit according to claim 12, wherein a display portion of the display device comprises a thin film transistor, and the memory circuit is formed integrally with the display portion.

14. The memory circuit according to claim 12, wherein the display device is a liquid crystal display device.

15. The memory circuit according to claim 12, wherein the display device is an EL display device.

16. The memory circuit according to claim 12, wherein the display device is an EL display device having a means for displaying gray scales by using a subframe.

17. The memory circuit according to claim 12, wherein the display device is incorporated in at least one selected from the group consisting of a digital camera, a digital camera, a personal computer, a portable information terminal, an image reproduction device, a folding portable display device, a watch type communicator, and a mobile phone.

2. A memory circuit comprising:

a word line, a plurality of memory cells, and a driver circuit connected to the word line,

wherein the driver circuit includes a level shift circuit, and

wherein an output amplitude of the level shift circuit is larger than an output amplitude of the memory cell.

19. The memory circuit according to claim 2, wherein the memory circuit is a SRAM.

24. The memory circuit according to claim 2, wherein the memory circuit is a DRAM.

29. The memory circuit according to claim 2, wherein the memory circuit is a mask ROM.

34. The memory circuit according to claim 2, wherein the memory circuit comprises a thin film transistor.

39. The memory circuit according to claim 2, wherein the memory circuit is incorporated in a display device.

44. The memory circuit according to claim 39, wherein a display portion of the display device comprises a thin film transistor, and the memory circuit is formed integrally with the display portion.

49. The memory circuit according to claim 39, wherein the display device is a liquid crystal display device.

54. The memory circuit according to claim 39, wherein the display device is an EL display device.

59. The memory circuit according to claim 39, wherein the display device is an EL display device having a means for displaying gray scales by using a subframe.

64. The memory circuit according to claim 39, wherein the display device is incorporated in at least one selected from the group consisting of a digital camera, a digital camera, a personal computer, a portable information terminal, an image reproduction device, a folding portable display device, a watch type communicator, and a mobile phone.

3. A memory circuit comprising:

a word line, a plurality of memory cells, and a driver circuit connected to the word line,

wherein the driver circuit includes a level shift circuit, and

wherein an output amplitude of the level shift circuit is smaller than an output amplitude of the memory cell.

20. The memory circuit according to claim 3, wherein the memory circuit is a SRAM.

25. The memory circuit according to claim 3, wherein the memory circuit is a DRAM.

30. The memory circuit according to claim 3, wherein the memory circuit is a mask ROM.

35. The memory circuit according to claim 3, wherein the memory circuit comprises a thin film transistor.

40. The memory circuit according to claim 3, wherein the memory circuit is incorporated in a display device.

45. The memory circuit according to claim 40, wherein a display portion of the display device comprises a thin film transistor, and the memory circuit is formed integrally with the display portion.

50. The memory circuit according to claim 40, wherein the display device is a liquid crystal display device.

55. The memory circuit according to claim 40, wherein the display device is an EL display device.

60. The memory circuit according to claim 40, wherein the display device is an EL display device having a means for displaying gray scales by using a subframe.

65. The memory circuit according to claim 40, wherein the display device is incorporated in at least one selected from the group consisting of a digital camera, a digital camera, a personal computer, a portable information terminal, an image reproduction device, a folding portable display device, a watch type communicator, and a mobile phone.

4. A memory circuit comprising:

a word line, a plurality of memory cells, and a driver circuit connected to the word line,

wherein the driver circuit includes a level shift circuit, and

wherein the level shift circuit has a means for varying an output amplitude.

6. The memory circuit according to claim 4, wherein an output amplitude of the level shift circuit is controlled by a CPU.

21. The memory circuit according to claim 4, wherein the memory circuit is a SRAM.

26. The memory circuit according to claim 4, wherein the memory circuit is a DRAM.

31. The memory circuit according to claim 4, wherein the memory circuit is a mask ROM.

36. The memory circuit according to claim 4, wherein the memory circuit comprises a thin film transistor.

41. The memory circuit according to claim 4, wherein the memory circuit is incorporated in a display device.

46. The memory circuit according to claim 41, wherein a display portion of the display device comprises a thin film transistor, and the memory circuit is formed integrally with the display portion.

51. The memory circuit according to claim 41, wherein the display device is a liquid crystal display device.

56. The memory circuit according to claim 41, wherein the display device is an EL display device.

61. The memory circuit according to claim 41, wherein the display device is an EL display device having a means for displaying gray scales by using a subframe.

66. The memory circuit according to claim 41, wherein the display device is incorporated in at least one selected from the group consisting of a digital camera, a digital camera, a personal computer, a portable information terminal, an image reproduction device, a folding portable display device, a watch type communicator, and a mobile phone.

5. A memory circuit comprising:

a word line, a plurality of memory cells, and a driver circuit connected to the word line,

wherein the driver circuit includes a level shift circuit, and

wherein the level shift circuit has a means for varying an output amplitude when writing and reading.

18. The memory circuit according to claim 5, wherein an output amplitude of the level shift circuit is controlled by a CPU.

22. The memory circuit according to claim 5, wherein the memory circuit is a SRAM.

27. The memory circuit according to claim 5, wherein the memory circuit is a DRAM.

32. The memory circuit according to claim 5, wherein the memory circuit is a mask ROM.

37. The memory circuit according to claim 5, wherein the memory circuit comprises a thin film transistor.

42. The memory circuit according to claim 5, wherein the memory circuit is incorporated in a display device.

47. The memory circuit according to claim 42, wherein a display portion of the display device comprises a thin film transistor, and the memory circuit is formed integrally with the display portion.

52. The memory circuit according to claim 42, wherein the display device is a liquid crystal display device.

57. The memory circuit according to claim 42, wherein the display device is an EL display device.

62. The memory circuit according to claim 42, wherein the display device is an EL display device having a means for displaying gray scales by using a subframe.

67. The memory circuit according to claim 42, wherein the display device is incorporated in at least one selected from the group consisting of a digital camera, a digital camera, a personal computer, a portable information terminal, an image reproduction device, a folding portable display device, a watch type communicator, and a mobile phone.

7. A memory circuit comprising:

a word line, a plurality of memory cells, and a driver circuit connected to the word line,

wherein the driver circuit includes a level shift circuit, and

wherein an output amplitude of the level shift circuit in writing is larger than an output amplitude in reading.

23. The memory circuit according to claim 7, wherein the memory circuit is a SRAM.

28. The memory circuit according to claim 7, wherein the memory circuit is a DRAM.

33. The memory circuit according to claim 7, wherein the memory circuit is a mask ROM.

38. The memory circuit according to claim 7, wherein the memory circuit comprises a thin film transistor.

43. The memory circuit according to claim 7, wherein the memory circuit is incorporated in a display device.

48. The memory circuit according to claim 43, wherein a display portion of the display device comprises a thin film transistor, and the memory circuit is formed integrally with the display portion.

53. The memory circuit according to claim 43, wherein the display device is a liquid crystal display device.

58. The memory circuit according to claim 43, wherein the display device is an EL display device.

63. The memory circuit according to claim 43, wherein the display device is an EL display device having a means for displaying gray scales by using a subframe.

68. The memory circuit according to claim 43, wherein the display device is incorporated in at least one selected from the group consisting of a digital camera, a digital camera, a personal computer, a portable information terminal, an image reproduction device, a folding portable display device, a watch type communicator, and a mobile phone.