Method and system for an integrated dual port gigabit Ethernet controller chip

• US 20050013317A1
• Filed: 07/08/2004
• Published: 01/20/2005
• Est. Priority Date: 07/14/2003
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Lindsay, Steven B., Alvstad, Gary
• Granted Patent: US 8,923,307 B2
• Time in Patent Office: Days
• US Class Current: 370/462
• CPC Class Codes: H04L 12/28 characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks] wireless communication networks H04W ; arrangements for dividing the transmission path H04W40/00
• CPC Class Codes: H04L 12/40013 Details regarding a bus controller
• CPC Class Codes: H04L 49/9063 Intermediate storage in different physical parts of a node or terminal

Abstract

Aspects of the invention may include a dual port Ethernet controller having a bus interface, a first Ethernet controller coupled to the bus interface such as a PCI bus interface and a second Ethernet controller coupled to the bus interface. The first Ethernet controller, second Ethernet controller and bus interface are integrated within a single chip. The dual port Ethernet controller may also include an arbiter, which is coupled to the first Ethernet controller, the second Ethernet controller and the bus interface. A plurality of shared resources may be coupled to one or more of the first Ethernet controller, the second Ethernet controller and the arbiter. The shared resources may include, but is not limited to, a non-volatile memory 304 and a general purpose input/out interface.

Claims

1. A method for processing network data, the method comprising:

receiving data by a first Ethernet controller integrated within a chip;

receiving data by a second Ethernet controller integrated within said chip; and

arbitrating which one of said first Ethernet controller and said second Ethernet controller can transfer data over a single bus interface integrated within said chip.

2. The method according to claim 1, further comprising acknowledging a successful arbitration to one of said first Ethernet controller and said second controller.

3. The method according to claim 2, further comprising:

if said first Ethernet controller receives said acknowledgement of said successful arbitration, transferring said received data from said first Ethernet controller to said integrated single bus interface; and

if said second Ethernet controller receives said acknowledgement of said successful arbitration, transferring said received data from said second Ethernet controller to said integrated single bus interface.

4. The method according to claim 3, further comprising:

tagging said data received from said first Ethernet controller with a first unique identifier; and

tagging said data received from said second Ethernet controller with a second unique identifier.

5. The method according to claim 1, further comprising receiving data from at least one device external to said chip and coupled to said integrated single bus interface.

6. The method according to claim 5, further comprising determining which one of said first Ethernet controller and said second Ethernet controller should receive said received data for processing.

7. The method according to claim 6, wherein said determining further comprises determining a first unique identifier identifying said received data to be processed by said first Ethernet controller.

8. The method according to claim 6, wherein said determining further comprises determining a second unique identifier identifying said received data to be processed by said second Ethernet controller.

9. The method according to claim 5, further comprising transferring said received data from said single integrated bus interface to at least one of said first Ethernet controller and said second Ethernet controller.

10. The method according to claim 9, further comprising independently processing said received data transferred to said first Ethernet controller by said first Ethernet controller and processing said received data transferred to said second Ethernet controller by said second Ethernet controller.

11. A dual port Ethernet controller;

comprising;

a bus interface;

a first Ethernet controller coupled to said bus interface; and

a second Ethernet controller coupled to said bus interface, said bus interface, said first Ethernet controller and said second Ethernet controller integrated within a single chip.

12. The dual port Ethernet controller according to claim 11, further comprising an arbiter coupled to said first Ethernet controller, said second Ethernet controller and said bus interface.

13. The dual port Ethernet controller according to claim 12, further comprising a shared resource interface coupled to at least one of said first Ethernet controller, said second Ethernet controller and said arbiter.

14. The dual port Ethernet controller according to claim 13, wherein said shared resource interface comprises at least one of a non-volatile memory and a general purpose input/out interface.

15. The dual port Ethernet controller according to claim 14, wherein said non-volatile memory further comprises at least one of an EEPROM, a Flash memory, a SMBus interface and a serial programming interface.

16. The dual port Ethernet controller according to claim 14, wherein said general purpose input/output interface further comprises at least one general purpose pin.

17. The dual port Ethernet controller according to claim 12, wherein at least one of said first Ethernet controller and said second Ethernet controller comprises:

an Ethernet transceiver;

a MAC controller coupled to said Ethernet transceiver;

a DMA controller coupled to at least one of said MAC controller and said arbiter;

a memory coupled to said MAC controller;

a transmit CPU coupled to at least one of said MAC controller and said memory;

a receive CPU coupled to at least one of said MAC controller and said memory; and

at least one control and status register coupled to said at least one of said bus interface, said Ethernet transceiver, said MAC controller, said DMA controller, said memory, said transmit CPU and said receive CPU.

18. The dual port Ethernet controller according to claim 17, wherein said at least one control and status register comprises:

a bus interface register;

a status register; and

a control register.

19. The dual port Ethernet controller according to claim 17, wherein said at least one control and status register comprises a MII interface register.

20. The dual port Ethernet controller according to claim 11, wherein said bus interface is a PCI interface.

21. The dual port Ethernet controller according to claim 11, further comprising at least one of a clock generator and a phase lock loop integrated with said chip and coupled to at least one of said bus interface, said first Ethernet controller and said second Ethernet controller.

22. The dual port Ethernet controller according to claim 11, further comprising at least one LED interface integrated with said chip and coupled to at least one of said bus interface, said first Ethernet controller and said second Ethernet controller.

23. The dual port Ethernet controller according to claim 11, further comprising at least one debug interface integrated with said chip and coupled to at least one of said bus interface, said first Ethernet controller and said second Ethernet controller.

24. The dual port Ethernet controller according to claim 11, wherein said at least one debug interface is a JTAG interface.