Sequential unique marking

• US 20050014327A1
• Filed: 08/11/2004
• Published: 01/20/2005
• Est. Priority Date: 08/10/2001
• Status: Active Grant

• Current Assignee: James S. Raitter
• Original Assignee: James S. Raitter
• Inventors: Raitter, James S.
• Granted Patent: US 6,996,484 B2
• Time in Patent Office: Days
• US Class Current: 438/202
• CPC Class Codes: G01R 31/2893 Handling, conveying or loading, e.g. belts, boats, vacuum fingers G01R31/2867 takes precedence; handling semiconductor devices or wafers during manufacture or treatment H01L21/67
• CPC Class Codes: H01L 21/67294 using identification means, e.g. labels on substrates or labels on containers
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
• CPC Class Codes: H01L 2221/68313 Auxiliary support including a cavity for storing a finished device, e.g. IC package, or a partly finished device, e.g. die, during manufacturing or mounting
• CPC Class Codes: H01L 2223/54433 containing identification or tracking information
• CPC Class Codes: H01L 2223/54473 for use after dicing
• CPC Class Codes: H01L 2223/5448 Located on chip prior to dicing and remaining on chip after dicing
• CPC Class Codes: H01L 2223/54486 Located on package parts, e.g. encapsulation, leads, package substrate
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The present invention comprises a method of sequential unique marking comprising providing a multi-die handling device with a plurality of semiconductor devices therein, reading an ID code on the multi-die handling device, retrieving a tray map file corresponding to the ID code, determining a tray matrix of the multi-die handling device, retrieving data from the tray map file, the data comprising unique characters correlating to each semiconductor device of the plurality of semiconductor devices, and marking each semiconductor device with the data.

Claims

1. A method of uniquely marking a plurality of semiconductor devices in a multi-die handling device, comprising:

reading an ID code on the multi-die handling device;

retrieving a tray map file corresponding to the ID code;

retrieving from the tray map file, unique data corresponding to each semiconductor device of the plurality of semiconductor devices; and

marking each semiconductor device of the plurality of semiconductor devices with the unique data corresponding to each semiconductor device.

2. The method of claim 1, wherein marking further comprises marking each semiconductor device of the plurality of semiconductor devices with a non-unique marking, the non-unique marking including one or more items selected from the group consisting of semiconductor device data, date code, country code, and company logo.

3. The method of claim 1, wherein the unique data comprises characterization data indicating at least one device parameter for at least one semiconductor device of the plurality of semiconductor devices.

4. The method of claim 1, wherein the unique data comprises test data extracted from the tray map file for at least one semiconductor device of the plurality of semiconductor devices.

5. The method according to claim 1, wherein each semiconductor device of the plurality of semiconductor devices comprises an integrated circuit semiconductor device.

6. The method according to claim 1, wherein each semiconductor device of the plurality of semiconductor devices comprises a semiconductor device selected from the group consisting of Dynamic Random Access Memory (DRAM) semiconductor devices, Static Random Access Memory (SRAM) semiconductor devices, Synchronous DRAM (SDRAM) semiconductor devices, processor semiconductor devices, Single In-Line Memory Modules (SIMMs), and Dual In-Line Memory Modules (DIMMs).

7. The method of claim 1, wherein marking occurs before packaging each semiconductor device of the plurality of semiconductor devices.

8. The method of claim 1, wherein marking occurs after packaging each semiconductor device of the plurality of semiconductor devices.

9. A method of uniquely marking, comprising:

providing a multi-die handling device having a plurality of pockets configured in a matrix organization;

placing at least one semiconductor device in at least one pocket of the plurality of pockets of the multi-die handling device;

reading an ID code on the multi-die handling device;

retrieving a tray map file corresponding to the ID code;

retrieving from the tray map file, unique data corresponding to the at least one semiconductor device; and

marking the at least one semiconductor device with the unique data.

10. The method of claim 9, wherein the matrix organization comprises a single dimension.

11. The method of claim 9, wherein the matrix organization comprises two dimensions.

12. The method of claim 9, wherein the matrix organization comprises three dimensions.

13. The method of claim 9, wherein marking further comprises, marking the at least one semiconductor device with a non-unique marking including one or more items selected from the group consisting of semiconductor device data, date code, country code, and company logo.

14. The method of claim 9, wherein the unique data comprises characterization data indicating at least one device parameter for the at least one semiconductor device.

15. The method of claim 9, wherein the unique data comprises test data extracted from the tray map file.

16. The method according to claim 9, wherein the at least one semiconductor device comprises a semiconductor device selected from the group consisting of Dynamic Random Access Memory (DRAM) semiconductor devices, Static Random Access Memory (SRAM) semiconductor devices, Synchronous DRAM (SDRAM) semiconductor devices, processor semiconductor devices, Single In-Line Memory Modules (SIMMs), and Dual In-Line Memory Modules (DIMMs).

17. The method of claim 9, wherein marking occurs before packaging the at least one semiconductor device.

18. The method of claim 9, wherein marking occurs after packaging the at least one semiconductor device.

19. A method of culling semiconductor devices, comprising:

retrieving a plurality of semiconductor devices from at least one reject bin;

providing at least one carrier having a plurality of pocket locations;

assigning the at least one carrier an ID code;

placing each semiconductor device of the plurality of semiconductor devices in a pocket location of the plurality of pocket locations;

testing each semiconductor device of the plurality of semiconductor devices;

generating a tray map file comprising test data corresponding to each semiconductor device of the plurality of semiconductor devices;

storing the tray map file in association with the ID code of the at least one carrier; and

marking each semiconductor device of the plurality of semiconductor devices with the corresponding test data.

20. The method of claim 19, wherein marking further comprises marking each semiconductor device of the plurality of semiconductor devices with a non-unique marking, the non-unique marking including one or more items selected from the group consisting of semiconductor device data, date code, country code, and company logo.

21. The method of claim 19, wherein the test data comprises characterization data indicating at least one device parameter for at least one semiconductor device of the plurality of semiconductor devices.

22. The method according to claim 19, wherein each semiconductor device of the plurality of semiconductor devices comprises a semiconductor device selected from the group consisting of Dynamic Random Access Memory (DRAM) semiconductor devices, Static Random Access Memory (SRAM) semiconductor devices, Synchronous DRAM (SDRAM) semiconductor devices, processor semiconductor devices, Single In-Line Memory Modules (SIMMs), and Dual In-Line Memory Modules (DIMMs).

23. The method of claim 19, wherein marking occurs before packaging each semiconductor device.

24. The method of claim 19, wherein marking occurs after packaging each semiconductor device.