Method of suppressing the effect of shining spots present at the edge of a wafer

• US 20050014364A1
• Filed: 07/18/2003
• Published: 01/20/2005
• Est. Priority Date: 07/18/2003
• Status: Abandoned Application

• Current Assignee: Infineon Technologies North America Corporation (Infineon Technologies AG), International Business Machines Corporation
• Original Assignee: Infineon Technologies North America Corporation (Infineon Technologies AG), International Business Machines Corporation
• Inventors: Randall, Mai, Cheng, Kangguo, Chen, Xiaochun Linda
• Application Number:
  US10/622,607
• Publication Number:
  US 20050014364A1
• Time in Patent Office: Days
• US Class Current: 438/671
• CPC Class Codes: H01L 21/3083 characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
• CPC Class Codes: H10B 12/0383 wherein the transistor is vertical
• CPC Class Codes: H10B 12/0387 Making the trench

Abstract

Devices formed in a substrate are protected from shining spots present in a periphery of the substrate. A ring of material is formed on the substrate to separate the periphery of the substrate from a further region of the substrate where the devices are formed.

Claims

1. A method of protecting devices formed in a substrate from shining spots present in a periphery of said substrate, said method comprising:

forming a ring of material atop said substrate to separate said periphery of said substrate from a further region of said substrate wherein said devices are formed.

2. The method of claim 1 wherein said forming step comprises forming said ring of material atop a hard mask layer that is disposed atop said substrate.

3. The method of claim 1 wherein said forming step comprises depositing material in a region between said periphery of said substrate and said further region of said substrate.

4. The method of claim 1 wherein said forming step comprises depositing material atop all of said substrate and then patterning said material to form said ring of material.

5. The method of claim 1 wherein said ring of material includes at least one of a resist layer and another organic material.

6. The method of claim 1 wherein said substrate is silicon.

7. A method of forming at least one device in a substrate, said method comprising:

depositing a layer of resist atop said substrate;

patterning said layer of resist to form a ring of resist atop said substrate, said ring of resist separating a periphery of said substrate from a further region of said substrate thereby protecting devices formed in said further region of said substrate from shining spots present in said periphery of said substrate;

depositing a further layer of resist atop said substrate and atop said ring of resist; and

patterning said further layer of resist to form at least one patterned region within said further region of said substrate.

8. The method of claim 7 further comprising:

depositing a pad oxide layer atop said substrate, depositing a pad nitride layer atop said pad oxide layer, and depositing a hard mask layer atop said nitride layer; and

wherein said forming step comprises forming said ring of material atop said hard mask layer.

9. The method of claim 8 further comprising:

etching said hard mask layer using said patterned further layer of resist and said ring of resist as an etch mask; and

etching at least one trench region in said substrate using said hard mask layer and said ring of resist as an etch mask.

10. The method of claim 9 wherein said ring of resist is of sufficient thickness that a region of said hard mask layer that is beneath said ring of resist remains after said trench region is etched.

11. The method of claim 7 wherein said ring of resist is of sufficient thickness that a region of said further layer of resist that is atop said ring of resist is not patterned during said step of patterning said further layer of resist.

12. The method of claim 7 wherein said layer of resist comprises a negative resist, and said layer of resist is patterned by exposing said ring of resist and then removing an unexposed portion of said resist.

13. The method of claim 7 wherein said layer of resist comprises a positive resist, and said layer of resist is patterned by exposing said layer of resist except for said ring of resist and then removing an exposed portion of said resist.

14. The method of claim 7 wherein said substrate is silicon.

15. A semiconductor device formed in a substrate, said semiconductor device being formed by a method comprising:

depositing a layer of resist atop said substrate;

patterning said layer of resist to form a ring of resist atop said substrate, said ring of resist defining a separation region that separates a periphery of said substrate from a further region of said substrate thereby protecting devices formed in said further region of said substrate from shining spots present in said periphery of said substrate;

depositing a further layer of resist atop said substrate; and

patterning said further layer of resist to form at least one patterned region within said further region of said substrate.

16. The semiconductor device of claim 15 wherein said method further comprises:

depositing a pad oxide layer atop said substrate, depositing a pad nitride layer atop said pad oxide layer, and depositing a hard mask layer atop said nitride layer; and

wherein said forming step comprises forming said ring of material atop said hard mask layer.

17. The semiconductor device of claim 16 wherein said method further comprises:

etching said hard mask layer using said patterned further layer of resist and said ring of resist as an etch mask; and

etching at least one trench region in said substrate using said hard mask layer and said ring of resist as an etch mask.

18. The semiconductor device of claim 17 wherein said ring of resist is of sufficient thickness that a region of said hard mask layer that is beneath said ring of resist remains after said trench region is etched.

19. The semiconductor device of claim 15 wherein said ring of resist is of sufficient thickness that a region of said further layer of resist that is atop said ring of resist is not patterned during said step of patterning said further layer of resist.

20. The semiconductor device of claim 15 wherein said layer of resist comprises a negative resist, and said layer of resist is patterned by exposing said ring of resist and then removing an unexposed portion of said resist.

21. The semiconductor device of claim 15 wherein said layer of resist comprises a positive resist, and said layer of resist is patterned by exposing said layer of resist except for said ring of resist and then removing an exposed portion of said resist.

22. The semiconductor device of claim 15 wherein said substrate is silicon.

23. A method of forming at least one device in a substrate, said method comprising:

depositing a pad oxide layer atop said substrate;

depositing a pad nitride layer atop said pad oxide layer;

depositing a hard mask layer atop said nitride layer;

depositing a layer of resist atop said hard mask layer;

patterning said layer of resist to form a ring of resist, said ring of resist separating a periphery of said substrate from a further region of said substrate thereby protecting devices formed in said further region of said substrate from shining spots present in said periphery of said substrate;

depositing a further layer of resist atop said hard mask layer and atop said ring of resist;

patterning said further layer of resist to form at least one patterned region within said further region of said substrate, said ring of resist being of sufficient thickness that a region of said further layer of resist that is atop said ring of resist is not patterned;

etching said hard mask layer using said patterned further layer of resist and said ring of resist as an etch mask; and

etching at least one trench region in said substrate using said hard mask layer and said ring of resist as an etch mask, said ring of resist being of sufficient thickness that a region of said hard mask layer that is beneath said ring of resist remains after said trench region is etched.

24. A semiconductor device formed in a substrate, said semiconductor device being formed by a method comprising:

depositing a pad oxide layer atop said substrate;

depositing a pad nitride layer atop said pad oxide layer;

depositing a hard mask layer atop said nitride layer;

depositing a layer of resist atop said hard mask layer;

patterning said layer of resist to form a ring of resist, said ring of resist defining a separation region that separates a periphery of said substrate from a further region of said substrate thereby protecting devices formed in said further region of said substrate from shining spots present in said periphery of said substrate;

depositing a further layer of resist atop said hard mask layer and atop said ring of resist;

patterning said further layer of resist to form at least one patterned region within said further region of said substrate, said ring of resist being of sufficient thickness that a region of said further layer of resist that is atop said ring of resist is not patterned;

etching said hard mask layer using said patterned further layer of resist and said ring of resist as an etch mask; and

etching at least one trench region in said substrate using said hard mask layer and said ring of resist as an etch mask, said ring of resist being of sufficient thickness that a region of said hard mask layer that is beneath said ring of resist remains after said trench region is etched.

25. A semiconductor device structure formed in a substrate, said semiconductor device structure comprising:

a separation region that separates at least one device region from a periphery of the substrate having shining spots formed therein.