Synchronous data serialization circuit
First Claim
1. A data processing circuit comprising;
- a first clocked data storage circuit receiving a first data bit and a clock signal, the first clocked data storage circuit having a first stored output for transmitting a first stored data bit;
a delay circuit receiving a second data bit, the delay circuit transmitting a delayed data signal;
a second clocked data storage circuit receiving the delayed data signal and the clock signal, the second clocked data storage circuit having a second storage output for transmitting a second stored data bit; and
a multiplexer having a first output coupled to the first stored output, a second input coupled to the second stored output, and a select input coupled to the clock signal.
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Abstract
In accordance with the present invention a data processing circuit includes a first data path for processing first data. The first data path includes a first data storage circuit. A second data path is provided for processing second data. The second data path includes a second data storage circuit. A multiplexer having a first input coupled to the first data path and a second input coupled to the second data path receives the stored values. The multiplexer includes a select input coupled to a clock signal. A delay circuit is configured to delay storage of the second data in the second data storage circuit, wherein the first data storage circuit stores the first data in response to receiving a first timing signal, and the second data storage circuit stores the second data in response to receiving a second timing signal.
19 Citations
2 Claims
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1. A data processing circuit comprising;
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a first clocked data storage circuit receiving a first data bit and a clock signal, the first clocked data storage circuit having a first stored output for transmitting a first stored data bit;
a delay circuit receiving a second data bit, the delay circuit transmitting a delayed data signal;
a second clocked data storage circuit receiving the delayed data signal and the clock signal, the second clocked data storage circuit having a second storage output for transmitting a second stored data bit; and
a multiplexer having a first output coupled to the first stored output, a second input coupled to the second stored output, and a select input coupled to the clock signal.
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2-30. -30 (Cancelled)
Specification