Method and circuit for generating a tracking error signal using differential phase detection
First Claim
1. A method for generating a tracking error signal using differential phase detection, comprising:
- reading a plurality of splitting signals, which are inducted by a quadrant photodetector and read by a pick-up, wherein said plurality of splitting signals are further equally divided into two groups signals and at least one signal comprised in each group being mixed;
generating a plurality of up clock signals and a plurality of down clock signals, wherein said plurality of splitting signals and said two groups signals are connected to a plurality of phase detectors, and said plurality of phase detectors generate said up clock signals and said down clock signals;
processing said plurality of up clock signals and said plurality of down clock signals, wherein said up clock signals are processed to obtain a up signal and said down clock signals are processed to obtain a down signal for eliminating phase difference caused by circuit; and
outputting a tracking error signal obtained by comparing said up signal and said down signal.
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Abstract
A circuit for generating tracking error signal using differential phase detection, comprising a quadrant photodetector for receiving optical signal and inducting splitting signal A, splitting signal B, splitting signal C and splitting signal D, two adders for generating group signal (A+C) and group signal (B+D). A plurality of equalizers for receiving, equalizing and amplifying splitting signal A, splitting signal B, splitting signal C, splitting signal D, group signal (A+C) and group signal (B+D). A plurality of phase detectors for receiving the output of equalizers and comparing phase difference of splitting signal A and group signal (A+C), group signal (A+C) and splitting signal B, splitting signal C and group signal (B+D), and group signal (B+D) and splitting signal D, and outputting a plurality of adjustment signals respectively. A circuit for eliminating the phase difference by adding and subtracting some adjustment signals with same phase difference. A comparator for receiving and comparing the output of the circuit to obtain a tracking error signal.
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Citations
20 Claims
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1. A method for generating a tracking error signal using differential phase detection, comprising:
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reading a plurality of splitting signals, which are inducted by a quadrant photodetector and read by a pick-up, wherein said plurality of splitting signals are further equally divided into two groups signals and at least one signal comprised in each group being mixed;
generating a plurality of up clock signals and a plurality of down clock signals, wherein said plurality of splitting signals and said two groups signals are connected to a plurality of phase detectors, and said plurality of phase detectors generate said up clock signals and said down clock signals;
processing said plurality of up clock signals and said plurality of down clock signals, wherein said up clock signals are processed to obtain a up signal and said down clock signals are processed to obtain a down signal for eliminating phase difference caused by circuit; and
outputting a tracking error signal obtained by comparing said up signal and said down signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A circuit for generating a tracking error signal using differential phase detection, comprising:
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a quadrant photodetector for receiving an optical signal and generating a splitting signal A, a splitting signal B, a splitting signal C and a splitting signal D, wherein said splitting signal A adding said splitting signal C by an adder for forming a group signal (A+C), and said splitting signal B adding said splitting signal D by another adder for forming a group signal (B+D);
a plurality of equalizer for receiving, equalizing and amplifying said splitting signal A, said splitting signal B, said splitting signal C, said splitting signal D, said group signal (A+C) and said group signal (B+D);
a plurality of phase detectors for receiving output of said plurality of equalizers, comparing phase difference between said splitting signal A and said group signal (A+C), said group signal (A+C) and said splitting signal B, said splitting signal C and said group signal (B+D), and said group signal (B+D) and said splitting signal D, and outputting a plurality of adjusting signals respectively;
a treating circuit for comparing said plurality of adjusting signals outputted by said plurality of phase detectors to obtain an up signal and a down signal;
a plurality of low pass filters for eliminating the high frequency noise of said up signal and down signal; and
a comparator for comparing said up signal and down signal to obtain a tracking error signal. - View Dependent Claims (10, 11, 12, 13)
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14. A circuit for generating a tracking error signal using differential phase detection comprises:
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a first equalizer for receiving a splitting signal A generated by a quadrant photodetector and equalizing and amplifying said splitting signal A;
a second equalizer for receiving a splitting signal B generated by a quadrant photodetector and equalizing and amplifying said splitting signal B;
a third equalizer for receiving a splitting signal C generated by a quadrant photodetector and equalizing and amplifying said splitting signal C;
a fourth equalizer for receiving a splitting signal D generated by a quadrant photodetector and equalizing and amplifying said splitting signal D;
a fifth equalizer for receiving a group signal (A+C) and equalizing and amplifying said group signal (A+C), wherein said group signal (A+C) is formed by adding said splitting signal A and said splitting signal B by another adder;
a sixth equalizer for receiving a group signal (B+D) and equalizing and amplifying said group signal (B+D), wherein said group signal (B+D) is formed by adding said splitting signal B and said splitting signal D by another adder;
a first phase detector for receiving and comparing said splitting signal A and said group signal (A+C) and outputting an up clock signal and a down clock signal, wherein said splitting signal A being outputted from said first equalizer and said group signal (A+C) being outputted from said fifth equalizer;
a second phase detector for receiving and comparing said splitting signal (A+C) and said group signal B and outputting an up clock signal and a down clock signal, wherein said group signal (A+C) being outputted from said fifth equalizer and said splitting signal B being outputted from said second equalizer;
a third phase detector for receiving and comparing said splitting signal C and said group signal (B+D) and outputting an up clock signal and a down clock signal, wherein said splitting signal C being outputted from said third equalizer and said group signal (B+D) being outputted from said sixth equalizer;
a fourth phase detector for receiving and comparing said group signal (B+D) and said splitting signal D and outputting an up clock signal and a down clock signal, wherein said group signal (B+D) being outputted from said sixth equalizer and said splitting signal D being outputted from said fourth equalizer;
a treating circuit for processing and comparing said plurality of up clock signals and down clock signals outputted by said plurality of phase detectors to obtain an up signal and a down signal, said up signal being obtained by adding up clock signal outputted by said first phase detector and up clock signal outputted by said second phase detector and then subtracting the result of adding up clock signal of said third phase detector and that of said fourth phase detector, said down signal being obtained by adding down clock signal outputted by said first phase detector and down clock signal outputted by said second phase detector and then subtracting the result of adding down clock signal of said third phase detector and that of said fourth phase detector;
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a first low pass filter for receiving said up signal;
a second low pass filter for receiving said down signal; and
a comparator for comparing output signal of said first low pass filter and said second low pass filter and generating a tracking error signal. - View Dependent Claims (15, 16, 17, 18, 19, 20)
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Specification