Phase shifter with reduced linear dependency
First Claim
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1. A method for generating a phase shifter network, comprising:
- providing a linear finite state machine, the linear finite state machine comprising a plurality of cells;
providing a first combination of cells from the plurality of cells, the first combination of cells providing a first plurality of sequences to be sent to a circuit under test;
generating at least one second combination of cells from the plurality of cells to provide at least one second plurality of sequences to be sent to the circuit under test;
determining whether the at least one second plurality of sequences overlaps with the first plurality of sequences; and
generating a linear phase shifter based on whether the at least one second plurality of sequences overlaps with the first plurality of sequences.
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Abstract
A method is disclosed for the automated synthesis of phase shifters. Phase shifters comprise circuits used to remove effects of structural dependencies featured by pseudo-random test pattern generators driving parallel scan chains. Using a concept of duality, the method relates the logical states of linear feedback shift registers (LFSRs) and circuits spacing their inputs to each of the output channels. The method generates a phase shifter network balancing the loads of successive stages of LFSRs and satisfying criteria of reduced linear dependency, channel separation and circuit complexity.
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Citations
19 Claims
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1. A method for generating a phase shifter network, comprising:
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providing a linear finite state machine, the linear finite state machine comprising a plurality of cells;
providing a first combination of cells from the plurality of cells, the first combination of cells providing a first plurality of sequences to be sent to a circuit under test;
generating at least one second combination of cells from the plurality of cells to provide at least one second plurality of sequences to be sent to the circuit under test;
determining whether the at least one second plurality of sequences overlaps with the first plurality of sequences; and
generating a linear phase shifter based on whether the at least one second plurality of sequences overlaps with the first plurality of sequences. - View Dependent Claims (2, 3, 4)
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5. A method, comprising:
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providing an integrated circuit to be tested, the integrated circuit capable of receiving scan chains;
providing a linear finite state machine (LFSM) having a balanced load; and
generating a linear phase shifter, the linear phase shifter working in combination with the LFSM to send a plurality of scan chains to the integrated circuit to be tested. - View Dependent Claims (6, 7, 8, 9, 10, 11)
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12. One or more computer-readable media having computer-executable instructions for performing a method of processing memory elements, the method comprising:
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preprocessing a plurality of memory elements; and
generating a plurality of XOR taps from the plurality of memory elements, wherein generating the plurality of XOR taps comprises;
generating pseudo-random integers uniformly distributed in a given range; and
filling in a vector to produce a plurality of sequences chosen from an element set using the pseudo-random integers. - View Dependent Claims (13, 14)
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15. One or more computer-readable media having computer-executable instructions for performing a method of synthesizing phase shifters, the method comprising:
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generating a plurality of XOR taps combinations; and
adding at least one of the plurality of XOR taps combinations and a corresponding guard combination to a list. - View Dependent Claims (16, 17)
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18. An apparatus, comprising:
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means for providing a linear finite state machine having multiple memory elements coupled together, the memory elements having outputs for driving the linear phase shifter;
means for analyzing loading of outputs of memory elements to determine loading information indicating the loading of memory elements;
means for generating the linear phase shifter using the loading information, the linear phase shifter having linear logic gates coupled to the outputs of the multiple memory elements; and
means for coupling the linear phase shifter to multiple scan chains used for testing the integrated circuit.
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19. One or more computer-readable media having computer-executable instructions for performing a method comprising:
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providing a linear finite state machine having multiple memory elements coupled together, the memory elements having outputs for driving the linear phase shifter;
analyzing loading of outputs of memory elements to determine loading information indicating the loading of memory elements;
generating the linear phase shifter using the loading information, the linear phase shifter having linear logic gates coupled to the outputs of the multiple memory elements; and
coupling the linear phase shifter to multiple scan chains used for testing the integrated circuit.
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Specification