Gettering using voids formed by surface transformation
First Claim
1. A method for creating a gettering site in a semiconductor wafer, comprising:
- forming a predetermined arrangement of a plurality of holes in the semiconductor wafer through a surface of the wafer; and
annealing the wafer such that the wafer undergoes a surface transformation to transform the arrangement of the plurality of holes into a predetermined arrangement of at least one empty space within the wafer, the at least one empty space having a predetermined size, wherein the at least one empty space forms the gettering site.
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Accused Products
Abstract
One aspect of this disclosure relates to a method for creating a gettering site in a semiconductor wafer. In various embodiments, a predetermined arrangement of a plurality of holes is formed in the semiconductor wafer through a surface of the wafer. The wafer is annealed such that the wafer undergoes a surface transformation to transform the arrangement of the plurality of holes into a predetermined arrangement of at least one empty space of a predetermined size within the wafer to form the gettering site. One aspect relates to a semiconductor wafer. In various embodiments, the wafer includes at least one device region, and at least one gettering region located proximate to the at least one device region. The gettering region includes a precisely-determined arrangement of a plurality of precisely-formed voids that are formed within the wafer using a surface transformation process. Other aspects and embodiments are provided herein.
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Citations
73 Claims
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1. A method for creating a gettering site in a semiconductor wafer, comprising:
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forming a predetermined arrangement of a plurality of holes in the semiconductor wafer through a surface of the wafer; and
annealing the wafer such that the wafer undergoes a surface transformation to transform the arrangement of the plurality of holes into a predetermined arrangement of at least one empty space within the wafer, the at least one empty space having a predetermined size, wherein the at least one empty space forms the gettering site. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method for creating a proximity gettering site in a silicon wafer, comprising:
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forming a predetermined arrangement of a plurality of holes in the silicon wafer through a surface of the wafer; and
annealing the wafer such that the wafer undergoes a surface transformation to transform the arrangement of the plurality of holes into a predetermined arrangement of at least one void within a volume of the wafer, the at least one void having a predetermined size and an interior surface with dangling bonds, wherein the at least one void forms the gettering site and the at least one void has a predetermined shape and arrangement to have a large ratio between the interior surface and the volume. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17)
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18. A method for forming a semiconductor structure, comprising:
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precisely forming a plurality of holes through a surface of a semiconductor substrate in a precise arrangement;
annealing the semiconductor substrate such that the plurality of holes are transformed into at least one predetermined void in a gettering region within the semiconductor substrate; and
performing semiconductor fabrication processes to form a semiconductor device in a device region proximate to the gettering region, wherein defects generated by the at least one void getters unwanted impurities from the device region during the semiconductor fabrication processes. - View Dependent Claims (19, 20, 21, 22, 23, 24, 25)
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26. A method for forming a silicon structure, comprising:
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precisely forming a plurality of holes through a surface of a silicon substrate in a precise arrangement;
annealing the crystalline semiconductor such that the plurality of holes are transformed into at least one predetermined void in a gettering region within the semiconductor; and
performing semiconductor fabrication processes to form a semiconductor device in a device region proximate to the gettering region, wherein defects generated by the at least one void getters unwanted impurities from the device region during the subsequent semiconductor fabrication processes. - View Dependent Claims (27, 28, 29, 30, 31, 32, 33)
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34. A method for preparing a wafer for semiconductor device fabrication:
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forming a predetermined arrangement of a plurality of holes in the semiconductor wafer through a surface of the wafer; and
annealing the wafer such that the plurality of holes are transformed into a predetermined arrangement of at least one void within a predetermined gettering volume in the wafer, the at least one void having a predetermined size and shape with an interior surface area, the predetermined arrangement, size and shape being selected to provide a large interior surface area to gettering volume ratio to enhance gettering of a device region in the wafer. - View Dependent Claims (35, 36, 37, 38)
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39. A method for forming a transistor, comprising:
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forming a proximity gettering region to be proximate to a crystalline semiconductor region in a wafer, the proximity gettering region including a precise arrangement of precisely-formed voids to getter impurities from the crystalline semiconductor region;
forming a gate dielectric over the crystalline semiconductor region;
forming a gate over the gate dielectric; and
forming a first diffusion region and a second diffusion region in the crystalline semiconductor region, the first and second diffusion regions being separated by a channel region formed in the crystalline semiconductor region between the gate and the proximity gettering region. - View Dependent Claims (40, 41, 42, 43, 44)
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45. A method for forming a memory device, comprising:
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forming a gettering region in a semiconductor substrate, the gettering region including a precise arrangement of precisely-formed voids to getter impurities from a crystalline semiconductor region of the substrate;
forming a memory array in the crystalline semiconductor region, including forming a plurality of memory cells in rows and column and forming at least one transistor for each of the plurality of memory cells;
forming a plurality of word lines, including connecting each word line to a row of memory cells;
forming a plurality of bit lines, including connecting each bit line to a column of memory cells; and
forming control circuitry, including forming word line select circuitry and bit line select circuitry for use to select a number of memory cells for writing and reading operations. - View Dependent Claims (46, 47)
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48. A semiconductor wafer, comprising:
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at least one device region; and
at least one gettering region located proximate to the at least one device region, the at least one gettering region including a precisely-determined arrangement of a plurality of precisely-formed voids formed within the wafer using a surface transformation process. - View Dependent Claims (49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59)
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60. A semiconductor structure, comprising:
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a gettering region proximate to a device region in a semiconductor wafer;
the gettering region including a precisely-determined arrangement of a plurality of precisely-formed voids through a surface transformation process, each of the voids having an interior surface that includes dangling bonds such that the plurality of voids getter impurities from the at least one device region;
a transistor formed using the device region, the transistor including a gate dielectric over the device region;
a gate over the gate dielectric; and
a first diffusion region and a second diffusion region formed in the device region, the first and second diffusion regions being separated by a channel region formed in the device region between the gate and the proximity gettering region. - View Dependent Claims (61, 62, 63, 64, 65)
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66. A memory device, comprising:
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at least one gettering region formed in a semiconductor substrate, the gettering region including a precise arrangement of precisely-formed voids to getter impurities from a crystalline semiconductor region of the substrate;
a memory array formed in the crystalline semiconductor region, including a plurality of memory cells formed in rows and columns, and at least one transistor for each of the plurality of memory cells;
a plurality of word lines, each word line being connected to a row of memory cells;
a plurality of bit lines, each bit line being connected to a column of memory cells; and
control circuitry, including word line select circuitry and bit line select circuitry to select a number of memory cells for writing and reading operations. - View Dependent Claims (67, 68, 69, 70, 71, 72, 73)
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Specification