Semiconductor component
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Accused Products
Abstract
In the case of the semiconductor component (1) according to the invention, the source regions (S), the body regions (B) and, if appropriate, the body contact regions (Bk) are in each case arranged in mesa regions (M) of adjacent trenches (30). In the edge region (R) of the cell array (Z) the insulation (GOX, FOX) of the underlying trench structures (30) by an insulating oxide layer (FOX) is comparatively thick and formed in the form of a field oxide (FOX) or thick oxide (FOX).
96 Citations
46 Claims
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1-23. -23. (Cancelled)
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24. A semiconductor component comprising:
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a semiconductor material region comprised of a trench structure transistor arrangement including a transistor cell array, the transistor cell array including a plurality of trench transistors arranged in a strip-type fashion in a plurality of trench structures;
the trench transistors comprising gate regions formed in the interior of the trench structures and electrically insulated from wall regions of the respective trench structures by an insulating oxide layer;
the trench transistors further comprising source regions and body regions arranged in mesa regions located between adjacent trench structures in the semiconductor material region, the source regions being disposed within respective body regions and having a common surface region with the respective body regions; and
a first edge region of the transistor cell array wherein the insulating oxide layer in end regions of the respective trench structures has a first layer thickness in the form of a field oxide, and the insulating oxide layer outside the first edge region has a second layer thickness in the form of a gate oxide, the first layer thickness greater than the second layer thickness. - View Dependent Claims (25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45)
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46. A semiconductor component having a transistor cell array in a semiconductor material region of the semiconductor component, the transistor cell array patterned in open fashion and comprising:
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a. a plurality of trench structures, each of the plurality of trench structures comprising an interior defined by wall regions of the trench structure, and each of the plurality of trench structures comprising an end region;
b. a plurality of mesa regions between the trench structures;
c. a plurality of trench transistors arranged in the plurality of trench structures (30), the plurality of trench transistors comprising (i) body regions arranged in the mesa regions between adjacent trench structures;
(ii) source regions arranged in the mesa regions between adjacent trench structures, each source regions contained in one of the body regions and each source region and body region having a common surface region; and
(iii) gate regions arranged on the interior of the trench structures, the gate regions electrically insulated from the wall regions of the respective trench structures by an insulating oxide layer;
wherein the insulating oxide in the end regions of the respective trench structures has a first layer thickness and the insulating oxide outside of the end regions has a second layer thickness, the first layer thickness greater than the second layer thickness, the insulating oxide in the end regions comprising a field oxide, and the insulating oxide outside of the end regions comprising a gate oxide.
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Specification