System and method of fabricating micro cavities

• US 20050017313A1
• Filed: 11/13/2003
• Published: 01/27/2005
• Est. Priority Date: 08/07/2002
• Status: Active Grant

• Current Assignee: Chang-Feng Wan
• Original Assignee: Chang-Feng Wan
• Inventors: Wan, Chang-Feng
• Granted Patent: US 7,429,495 B2
• Time in Patent Office: Days
• US Class Current: 257/415
• CPC Class Codes: B81B 2201/0264 Pressure sensors
• CPC Class Codes: B81B 2203/0118 Cantilevers
• CPC Class Codes: B81B 2203/0307 Anchors
• CPC Class Codes: B81B 2203/0384 sloped profile
• CPC Class Codes: B81B 2207/07 Interconnects
• CPC Class Codes: B81C 1/00095 Interconnects
• CPC Class Codes: B81C 1/00285 using materials for controlling the level of pressure, contaminants or moisture inside of the package, e.g. getters
• CPC Class Codes: B81C 1/00333 Aspects relating to packaging of MEMS devices, not covered by groups B81C1/00269 - B81C1/00325
• CPC Class Codes: B81C 2201/019 Bonding or gluing multiple substrate layers
• CPC Class Codes: G01L 9/0042 Constructional details associated with semiconductive diaphragm sensors, e.g. etching, or constructional details of non-semiconductive diaphragms details about the integration or bonding of piezoresistor in or on the diaphragm G01L9/0052 and G01L9/0057 respectively
• CPC Class Codes: H01G 5/16 using variation of distance between electrodes
• CPC Class Codes: H01G 5/40 Structural combinations of variable capacitors with other electric elements not covered by this subclass, the structure mainly consisting of a capacitor, e.g. RC combinations
• CPC Class Codes: H01L 29/82 controllable by variation of the magnetic field applied to the device

Abstract

A system and method for manufacturing micro cavities at the wafer level using a unique, innovative MEMS (MicroElectroMechanical Systems) process, wherein micro cavities are formed, with epoxy bonded single-crystalline silicon membrane as cap and deposited and/or electroplated metal as sidewall, on substrate wafers. The epoxy is also the sacrificial layer. It is totally removed from within the cavity through small etch access holes etched in the silicon cap before the etch access holes are sealed under vacuum. The micro cavities manufactured therein can be used as pressure sensors or for packaging MEMS devices under vacuum or inert environment. In addition, the silicon membrane manufactured therein can be used to manufacture RF switches.

Claims

1. A method of manufacturing a plurality of micro enclosures on a substrate wafer, comprising steps of:

(1) bonding a cap wafer to said substrate wafer with an adhesive layer;

(2) thinning said cap wafer to desired thickness;

(3) patterning and etching said cap wafer and said adhesive to form islands of layers of said cap wafer and said adhesive on said substrate wafer; and

(4) patterning and depositing at least one metal layer on said islands to form a sidewall around said islands.

2. The method of claim 1, further comprising the steps of:

(1) patterning and etching etch access holes in said cap wafer of said enclosures;

(2) removing said adhesive through said etch access holes from said enclosures; and

(3) sealing said etch access holes with deposited films.

3. The method of claim 1, wherein said step (3) of patterning and etching said cap wafer and said adhesive to form islands of layers of said cap wafer and said adhesive on said substrate wafer, further comprises the step of patterning and etching a center boss in said cap wafer.

4. The method of claim 1, wherein said etching is accomplished with high-density plasma that contains hydrogen or argon.

5. The method of claim 1, wherein said substrate wafer comprises one or more of following:

micro-electro-mechanical device,

polymeric sacrificial layer,

polymeric planarizing layer,

microelectronic circuit,

and electrical component,

prior to said bonding.

6. The method of claim 1, further comprising the step of depositing getters on said cap wafer prior to said step (1) of bonding a cap wafer to said substrate wafer with an adhesive layer and subsequent heat activation of said getters.

7. The method of claim 2, wherein at least one of said deposited films comprises gas gettering materials.

8. The method of claim 7, wherein said gettering materials comprise one or more of the following:

TiN_xO_y
TiZr_x
TiN_x

9. The method of claim 1, wherein said islands have holes for forming support posts within confines of said islands.

10. The substrate wafer in claim 1 comprises micro-electro-mechanical (MEMS) devices fabricated thereon prior to said bonding, said micro enclosures surround said MEMS devices.

11. The method of claim 2, wherein in said sealing is done under controlled gas pressure environment comprising high vacuum or inert gas.

12. The method of claim 2, wherein said enclosures form pressure transducers.

13. The method of claim 2, wherein said enclosures form vacuum or hermetic packaging.

14. The method of claim 2, wherein said removing said adhesive is by etching with oxygenated plasma.

15. Said etching in claim 14 further removes any organic polymer coating or sacrificial layer present in said enclosures.

16. The method of claim 1, wherein at least one high conductivity metal film is deposited on at least one surface of said cap wafer prior to said step (1).

17. The method of claim 1, wherein said depositing at least on metal layer is by physical vapor deposition, plating, electroplating, or chemical vapor deposition.

18. The method of claim 1 further comprises the steps of patterning and etching bosses after said step (2).

28. The method of claim 1, wherein said adhesive layer is disposed by spinning and said spinning is at speed of between 1500 rpm to 7000 rpm for less than 2 seconds.

29. The method of claim 1, wherein said adhesive layer comprises Abocast 50-24 epoxy resin from Abatron, Incorporated, Kenosha, Wis. 53144 USA.

19. A method of planarizing a wafer, comprising steps of:

coating said wafer with a thick epoxy layer;

curing said epoxy layer by heat or ultraviolet light; and

thinning said epoxy layer to the desired thickness by lapping, grinding or polishing.

20. The method of claim 19, wherein said thick epoxy layer fills holes, cavities, troughs, or underside space of suspended structures.

21. The method of claim 20, further comprising the step of placing said wafer under a vacuum during or after said coating.

22. A system for making small enclosures on a substrate wafer, comprising:

a means for bonding a cap wafer to said substrate wafer with an adhesive layer;

a means for thinning said cap wafer to desired thickness;

a means for patterning and etching said cap wafer and said adhesive to form islands of layers of said cap wafer and said adhesive on said substrate wafer; and

a means patterning and depositing at least one metal layer on said islands to form a sidewall around said islands.

23. A vacuum or hermetic packaging enclosure comprising

a sidewall formed from deposited film;

a top formed from epoxy bonded wafer; and

a substrate;

wherein said epoxy bonded wafer is bonded to and said deposited film is deposited on said substrate;

said epoxy-bonded wafer comprise etch access; and

said etch access holes are sealed with deposited films.

24. A stepping electrostatic actuator of a MEMS device, comprising:

a suspended electrode as part of a bridge or a cantilever and a fixed electrode on a substrate;

said fixed electrode directly below said suspended electrode;

wherein said fixed electrode forms a stair or a slope.

25. The stepping electrostatic actuator of claim 24, wherein said stair of said fixed electrode comprises a plurality of steps, said steps are electrically insulated from each other and can be biased individually or collectively.

26. The stepping electrostatic actuator of claim 24, wherein said stepping electrostatic actuator is a tunable Fabry-Perot interferometer or a light switch.

27. The stepping electrostatic actuator of claim 24, wherein said stepping electrostatic actuator is a tunable capacitor, a RF switch, or a DC electrical switch.