Semiconductor device, package structure thereof, and method for manufacturing the semiconductor device

• US 20050017346A1
• Filed: 06/10/2004
• Published: 01/27/2005
• Est. Priority Date: 06/13/2003
• Status: Active Grant

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Yamagata, Osamu
• Granted Patent: US 7,208,832 B2
• Time in Patent Office: Days
• US Class Current: 257/701
• CPC Class Codes: H01L 2223/54473 for use after dicing
• CPC Class Codes: H01L 2224/05001 Internal layers
• CPC Class Codes: H01L 2224/05008 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
• CPC Class Codes: H01L 2224/05022 the internal layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05569 the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/24011 Deposited, e.g. MCM-D type
• CPC Class Codes: H01L 2224/24225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/24226 the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
• CPC Class Codes: H01L 2224/2518 being disposed on at least two different sides of the body, e.g. dual array
• CPC Class Codes: H01L 2224/2919 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73204 : the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73253 : Bump and layer connectors
• CPC Class Codes: H01L 2224/73265 : Layer and wire connectors
• CPC Class Codes: H01L 2224/73267 : Layer and HDI connectors
• CPC Class Codes: H01L 2224/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
• CPC Class Codes: H01L 2224/8203 : Reshaping, e.g. forming vias
• CPC Class Codes: H01L 2224/83121 : Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
• CPC Class Codes: H01L 2224/8319 : Arrangement of the layer connectors prior to mounting
• CPC Class Codes: H01L 2224/83801 : Soldering or alloying
• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 23/544 : Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/24 : of an individual high density interconnect connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/16 : the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01018 : Argon [Ar]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01038 : Strontium [Sr]
• CPC Class Codes: H01L 2924/01039 : Yttrium [Y]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01056 : Barium [Ba]
• CPC Class Codes: H01L 2924/01061 : Promethium [Pm]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01087 : Francium [Fr]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/0665 : Epoxy resin
• CPC Class Codes: H01L 2924/07802 : not being an ohmic electrical conductor
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/1532 : the connection portion being formed on the die mounting surface of the substrate
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/19105 : in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/30107 : Inductance

Abstract

A semiconductor device includes a plurality of insulating layers laminated on a substrate to cover passive elements such as a capacitor, an inductor, and the like, and to fix an IC chip in a face up state in one of the insulating layers. The insulating layers have similar structures in each of which the passive element or the semiconductor chip is disposed in at the bottom, a plug is formed in the insulating layer to pass therethrough in the thickness direction for extending an electrode of one of these elements to the top surface, and a conductive layer is provided as wiring on the top surface of the insulating layer to be connected to the plugs for electrically connecting respective elements or rearranging the electrode position. Also, an insulating layer is provided on the top for protecting the semiconductor device and for providing an external connecting electrode.

Claims

1. A semiconductor device comprising:

a plurality of insulating layers provided on a substrate;

a face-up active element and a face-up passive element each of which is covered with one of the insulating layers; and

a wiring formed on one of the insulating layers;

wherein the active element and/or the passive element is connected to the wiring through said one of the insulating layers.

2. The semiconductor device according to claim 1, further comprising an external connecting electrode provided on the insulating layers disposed on the wiring.

3. The semiconductor device according to claim 2, wherein the wiring is formed on a lower insulating layer, and the external connecting electrode is formed on an upper insulating layer.

4. The semiconductor device according to claim 1, wherein the insulating layers has a connecting hole, and a conductor formed in each connecting hole for connecting the active element and/or the passive element to the wiring.

5. The semiconductor device according to claim 1, wherein the wiring constitutes an inductance element.

6. The semiconductor device according to claim 1, wherein the insulating layers include a first insulating layer covering a first passive element, and a second insulating layer covering a second passive element and a semiconductor chip, the second insulating layer being formed on the first insulating layer.

7. The semiconductor device according to claim 1, wherein the insulating layers include a first insulating layer covering a first passive element and a semiconductor chip, a second insulating layer formed on the first insulating layer, and a third insulating layer covering a second passive element, the third insulating layer being formed on the second insulating.

8. The semiconductor device according to claim 1, wherein the insulating layers include a first insulating layer covering a first passive element, a second insulating layer covering a second passive element, the second insulating layer being formed on the first insulating layer, and a third insulating layer covering a semiconductor chip, the third insulating layer being formed on the second insulating layer.

9. The semiconductor device according to claim 1, wherein a plurality of semiconductor chips is stacked and fixed.

10. The semiconductor device according to claim 1, wherein the substrate is a silicon substrate.

11. The semiconductor device according to claim 1, wherein each of the insulating layers comprises a photosensitive polyimide.

12. A package structure of a semiconductor device, comprising the semiconductor device according to claim 1, the semiconductor device being buried in an insulating layer, and an external connecting electrode formed on the insulating layer.

13. The package structure of the semiconductor device according to claim 12, further comprising another functional component mounted on the insulating layer.

14. A method for manufacturing a semiconductor device comprising the steps of:

forming an insulating layer on a substrate to cover an active element;

forming an insulating layer on the substrate to cover a passive element; and

forming a wiring on an insulating layer on the substrate so that the active element and/or the passive element is connected to the wiring through the insulating layer.

15. The method for manufacturing the semiconductor device according to claim 14, further comprising:

forming a connecting hole in the insulating layer disposed on the wiring; and

forming an external connecting electrode in the connecting hole so that the external connecting electrode is connected to the wiring through the insulating layer disposed on the wiring.

16. The method for manufacturing the semiconductor device according to claim 14, further comprising:

forming a connecting hole in the insulating layers; and

forming a conductor in the connecting hole so that the active element and/or the passive element is connected to the wiring.

17. The method for manufacturing the semiconductor device according to claim 14, further comprising forming an inductance element by using the wiring.

18. The method for manufacturing the semiconductor device according to claim 14, wherein the wiring and connections to the active element and the passive element are formed by plating.

19. The method for manufacturing the semiconductor device according to claim 14, wherein the insulating layers include a first insulating layer covering a first passive element, and a second insulating layer covering a second passive element and a semiconductor chip, the second insulating layer being formed on the first insulating layer.

20. The method for manufacturing the semiconductor device according to claim 14, wherein the insulating layers include a first insulating layer covering a first passive element and a semiconductor chip, a second insulating layer formed on the first insulating layer, and a third insulating layer covering a second passive element, the third insulating layer being formed on the second insulating layer.

21. The method for manufacturing the semiconductor device according to claim 14, wherein the insulating layers include a first insulating layer covering a first passive element, a second insulating layer covering a second passive element, the second insulating layer being formed on the first insulating layer, and a third insulating layer covering a semiconductor chip, the third insulating layer being formed on the second insulating.

22. The method for manufacturing the semiconductor device according to claim 14, wherein the semiconductor chip is fixed to the substrate by positioning the semiconductor chip while observing both an alignment target on the substrate or the insulating layers and an electrode of the semiconductor chip in the same visual field of a camera.

23. The method for manufacturing the semiconductor device according to claim 14, wherein a plurality of semiconductor chips is stacked and fixed.

24. The method for manufacturing the semiconductor device according to claim 14, further comprising grinding the back of the substrate with the surface covered with a protective sheet to thin the substrate.

25. The method for manufacturing the semiconductor device according to claim 14, wherein a separation groove is formed in the front surface of the substrate, and the substrate is ground up to the separation groove to produce the semiconductor device.

26. The method for manufacturing the semiconductor device according to claim 14, wherein the semiconductor chip is produced by a method for dividing a semiconductor wafer, the dividing method comprising:

thinning the semiconductor wafer by grinding the back of the semiconductor wafer opposite to the electrode surface thereof covered with a protective sheet;

bonding the semiconductor wafer covered with the protective sheet to a dicing sheet;

removing the protective sheet;

dicing the semiconductor wafer to produce the thinned semiconductor chip; and

fixing the semiconductor ship to the substrate.

27. The method for manufacturing the semiconductor device according to claim 14, wherein the substrate is a silicon substrate.

28. The method for manufacturing the semiconductor device according to claim 14, wherein the insulating layers comprise a photosensitive polyimide.