Water level processing method and structure to manufacture two kinds of bumps, gold and solder, on one wafer

• US 20050017355A1
• Filed: 05/27/2004
• Published: 01/27/2005
• Est. Priority Date: 05/27/2003
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Chou, Chien-Kang, Chou, Chiu-Ming, Lin, Chu-Fu, Lin, Li-Ren
• Granted Patent: US 8,674,507 B2
• Time in Patent Office: Days
• US Class Current: 257/738
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/0347 using a lift-off mask
• CPC Class Codes: H01L 2224/03912 the bump being used as a mask for patterning the bonding area
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/04073 Bonding areas specifically adapted for connectors of different types
• CPC Class Codes: H01L 2224/05073 Single internal layer
• CPC Class Codes: H01L 2224/05082 Two-layer arrangements
• CPC Class Codes: H01L 2224/05083 Three-layer arrangements
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/11462 Electroplating
• CPC Class Codes: H01L 2224/1147 using a lift-off mask
• CPC Class Codes: H01L 2224/11849 Reflowing
• CPC Class Codes: H01L 2224/11912 the bump being used as a mask for patterning other parts
• CPC Class Codes: H01L 2224/1308 being stacked
• CPC Class Codes: H01L 2224/13082 : Two-layer arrangements
• CPC Class Codes: H01L 2224/13099 : Material
• CPC Class Codes: H01L 2224/131 : with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13111 : Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/13139 : Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/13144 : Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13147 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/16145 : the bodies being stacked
• CPC Class Codes: H01L 2224/45099 : Material
• CPC Class Codes: H01L 2224/48091 : Arched
• CPC Class Codes: H01L 2224/48453 : of the interface with the bonding area
• CPC Class Codes: H01L 2224/48463 : the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
• CPC Class Codes: H01L 2224/731 : Location prior to the connecting process
• CPC Class Codes: H01L 2224/73207 : Bump and wire connectors
• CPC Class Codes: H01L 2224/81411 : Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/85444 : Gold (Au) as principal constituent
• CPC Class Codes: H01L 2225/0651 : Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00013 : Fully indexed content
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01011 : Sodium [Na]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01016 : Sulfur [S]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/05042 : Si3N4
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/14 : Integrated circuits

Abstract

A chip structure comprising a substrate, a plurality of wire bonding pads and a plurality of solder pads is provided. Gold bumps or gold pads can be formed on the wire bonding pads while solder bumps can be formed on the solder pads concurrently. Alternatively, both wire bonding pads and solder pads can be formed of the same metal stack.

Claims

1. A chip structure comprising:

a substrate comprising a plurality of bonding pads and a passivation layer overlying said bonding pads wherein said passivation layer comprises a plurality of openings through which said bonding pads are exposed;

a plurality of wire bonding pads disposed on a first subset of said plurality of bonding pads exposed through said openings and further comprising a gold bump on each of said wire bonding pads; and

a plurality of solder pads disposed on a second subset of said plurality of bonding pads not covered by said wire bonding pads.

2. The chip structure according to claim 1 further comprising:

semiconductor device structures formed in and on said substrate; and

a plurality of layers of metal interconnection lines connecting to said semiconductor device structures wherein said bonding pads are formed in a topmost metal layer.

3. The chip structure according to claim 1 wherein said gold bumps are connected to an external circuit though a plurality of bonding wires.

4. The chip structure according to claim 1 wherein said gold bumps are used as testing pads.

5. The chip structure according to claim 1 wherein each of said gold bumps has a thickness of between about 1 micron and 60 microns.

6. The chip structure according to claim 1 further comprising an active device, a passive device, or a metal interconnect underlying said gold bump.

7. The chip structure according to claim 1 wherein each of said wire bonding pads further comprises an adhesion/barrier layer underlying said gold bump and directly overlying said bonding pad.

8. The chip structure according to claim 7 wherein said adhesion layer comprises a titanium-tungsten alloy, tantalum, tantalum nitride, or titanium nitride.

9. The chip structure according to claim 1 wherein a thickness of said bonding pads is between about 0.1 micron and 3 microns.

10. The chip structure according to claim 1 wherein a surface layer of each of said solder pads comprises a solder bump.

11. The chip structure according to claim 10 wherein said solder bumps comprise a tin-lead alloy, a tin-silver alloy, a tin-silver-copper alloy, or any other unleaded solder material.

12. The chip structure according to claim 10 wherein said solder bumps are connected to an external circuit.

13. The chip structure according to claim 1 wherein each of said solder pads comprises an underbump metallization (UBM) layer and an overlying solder bump.

14. The chip structure according to claim 1 wherein each of said solder pads comprises:

an adhesion layer; and

a seed layer for electroplating sputtered onto said adhesion layer.

15. The chip structure according to claim 14 wherein a material comprising said adhesion layer is titanium, chromium, a chromium-copper alloy, or a titanium-tungsten alloy, or a combination of these materials.

16. The chip structure according to claim 14 wherein said seed layer for electroplating comprises copper.

17. The chip structure according to claim 14 wherein each of said solder pads further comprises a diffusion barrier layer disposed on said seed layer for electroplating.

18. The chip structure according to claim 17 wherein said diffusion barrier layer comprises nickel, tin, copper, a tin-copper composite layer, or a copper-nickel composite layer.

19. The chip structure according to claim 17 wherein each of said solder pads further comprises a solder wettable layer disposed on said diffusion barrier layer.

20. The chip structure according to claim 19 wherein said solder wettable layer comprises gold, copper, tin, a tin-lead alloy, or an unleaded solder material.

21. The chip structure according to claim 19 further comprising a plurality of solders disposed on said solder-wettable layer.

22. The chip structure according to claim 19 further comprising a plurality of solder bumps formed on said solder-wettable layer.

23. The chip structure according to claim 22 wherein said solder bumps comprise a tin-lead alloy, a tin-silver alloy, or a tin-silver-copper alloy or any other unleaded solder material.

24. The chip structure according to claim 1 wherein said bonding pads comprise copper, aluminum, or an aluminum alloy.

25. The chip structure according to claim 1 further comprising a post-passivation metal interconnect line overlying said passivation layer wherein said post-passivation metal interconnect line and said gold bumps comprise the same material.

26. The chip structure according to claim 25 wherein said post-passivation metal interconnect line through openings in said passivation layer connects a portion of the circuit under said passivation layer to other portions of said circuit under said passivation layer.

27. The chip structure according to claim 26 wherein said openings in said passivation layer are greater than 0.1 micron in diameter.

28. The chip structure according to claim 1 wherein said passivation layer further comprises a power bus, a signal bus, and a ground bus thereover wherein said power bus, said signal bus, and said ground bus are connected to a power source, a signal source, and a ground source, respectively, under said passivation layer through openings in said passivation layer and wherein said power bus, said signal bus, said ground bus, and said gold bumps are formed with a same type of material.

29. The chip structure according to claim 28 wherein said openings in said passivation layer are greater than 0.1 micron in diameter.

30. The chip structure according to claim 1 further comprising a redistribution layer overlying said passivation layer wherein said redistribution layer redistributes original positions of said bonding pads to specific other positions and wherein said redistribution layer and said gold bumps are formed of a same material.

31. The chip structure according to claim 1 wherein each of said solder pads comprises:

an adhesion layer on said bonding pad;

a seed layer on said adhesion layer; and

a diffusion barrier layer on said seed layer.

32. The chip structure according to claim 31 further comprising a reflowed solder bump over said diffusion barrier layer.

33. The chip structure according to claim 32 further comprising a solder wettable layer overlying said diffusion barrier layer and underlying said solder bump.

34. The chip structure according to claim 32 further comprising a non-reflowed solder bump over said diffusion barrier layer.

35. A chip structure comprising:

a semiconductor substrate including semiconductor device structures formed in and on said substrate;

a plurality of layers of metal interconnection lines connecting to said semiconductor device structures;

a plurality of bonding pads formed in a topmost metal layer;

a passivation layer overlying said bonding pads wherein said passivation layer comprises a plurality of openings through which said bonding pads are exposed;

a plurality of wire bonding pads disposed on a first subset of said plurality of bonding pads wherein a surface layer of each of said wire bonding pads comprises a gold bump; and

a plurality of solder pads disposed on a second subset of said plurality of bonding pads not covered by said wire bonding pads wherein a surface layer of each of said solder pads comprises a solder bump.

36. The chip structure according to claim 35 wherein said gold bumps are connected to an external circuit though a plurality of bonding wires and wherein said solder bumps are connected to said external circuit.

37. The chip structure according to claim 35 wherein said gold bumps are used as testing pads.

38. The chip structure according to claim 35 wherein each of said gold bumps has a thickness of between about 1 micron and 60 microns.

39. The chip structure according to claim 35 wherein each of said wire bonding pads further comprises an adhesion/barrier layer underlying said gold bump and directly overlying said bonding pad.

40. The chip structure according to claim 39 wherein said adhesion/barrier layer comprises a titanium-tungsten alloy, tantalum, tantalum nitride, or titanium nitride.

41. The chip structure according to claim 35 wherein each of said solder pads comprises an underbump metallization (UBM) layer.

42. The chip structure according to claim 35 wherein each of said solder pads further comprises an adhesion layer underlying said solder bump.

43. The chip structure according to claim 42 wherein said a material comprising said adhesion layer is titanium, chromium, a chromium-copper alloy, or a titanium-tungsten alloy, or a combination of these materials.

44. The chip structure according to claim 35 wherein each of said solder pads further comprises a diffusion barrier layer disposed between said solder bump and said adhesion layer.

45. The chip structure according to claim 44 wherein said diffusion barrier layer comprises nickel, copper, or a copper-nickel composite layer.

46. The chip structure according to claim 44 wherein each of said solder pads further comprises a solder wettable layer disposed between said solder bump and said diffusion barrier layer.

47. The chip structure according to claim 46 wherein said solder wettable layer comprises gold, copper, tin, a tin-lead alloy, or an unleaded solder material.

48. The chip structure according to claim 35 wherein said solder bumps comprise a tin-lead alloy, a tin-silver alloy, or a tin-silver-copper alloy or any other unleaded solder material.

49. The chip structure according to claim 35 further comprising a post-passivation metal interconnect line overlying said passivation layer wherein said post-passivation metal interconnect line and said gold bumps comprise the same material.

50. The chip structure according to claim 49 wherein said post-passivation metal interconnect line through openings in said passivation layer connects a portion of the circuit under said passivation layer to other portions of said circuit under said passivation layer.

51. The chip structure according to claim 50 wherein said openings in said passivation layer are greater than 0.1 micron in diameter.

52. The chip structure according to claim 35 wherein said passivation layer further comprises a power bus, a signal bus, and a ground bus thereover wherein said power bus, said signal bus, and said ground bus are connected to a power source, a signal source, and a ground source, respectively, under said passivation layer through openings in said passivation layer and wherein said power bus, said signal bus, said ground bus, and said gold bumps are formed with a same type of material.

53. The chip structure according to claim 52 wherein said openings in said passivation layer are greater than 0.1 micron in diameter.

54. A chip structure comprising:

a semiconductor substrate including semiconductor device structures formed in and on said substrate;

a plurality of layers of metal interconnection lines connecting to said semiconductor device structures;

a plurality of bonding pads formed in a topmost metal layer;

a passivation layer overlying said bonding pads wherein said passivation layer comprises a plurality of openings through which said bonding pads are exposed;

a plurality of wire bonding pads disposed on a first subset of said plurality of bonding pads wherein a surface layer of each of said wire bonding pads comprises a gold bonding pad; and

a plurality of solder pads disposed on a second subset of said plurality of bonding pads not covered by said wire bonding pads wherein a surface layer of each of said solder pads further comprises a solder bump.

55. The chip structure according to claim 54 wherein said gold bonding pads are connected to an external circuit though a plurality of bonding wires.

56. The chip structure according to claim 54 wherein said gold bonding pads are used as testing pads.

57. The chip structure according to claim 54 wherein each of said gold bonding pads has a thickness of between about 0.1 micron to 3.0 microns.

58. The chip structure according to claim 54 wherein each of said wire bonding pads further comprises an adhesion/barrier layer underlying said gold bonding pad and directly overlying said bonding pad.

59. The chip structure according to claim 58 wherein said adhesion/barrier layer comprises a titanium-tungsten alloy, tantalum, tantalum nitride, or titanium nitride.

60. The chip structure according to claim 54 wherein each of said solder bumps is between about 1 micron and 400 microns thick.

61. The chip structure according to claim 54 wherein said solder pads comprise gold.

62. The chip structure according to claim 54 wherein said solder bumps comprise a tin-lead alloy, a tin-silver alloy, or a tin-silver-copper alloy, or any other unleaded solder material.

63. The chip structure according to claim 54 further comprising a post-passivation metal interconnect line overlying said passivation layer wherein said post-passivation metal interconnect line and said gold bonding pads comprise the same material.

64. The chip structure according to claim 63 wherein said post-passivation metal interconnect line through openings in said passivation layer connects a portion of the circuit under said passivation layer to other portions of said circuit under said passivation layer.

65. The chip structure according to claim 64 wherein said openings in said passivation layer are greater than 0.1 micron in diameter.

66. The chip structure according to claim 54 wherein said passivation layer further comprises a power bus, a signal bus, and a ground bus thereover wherein said power bus, said signal bus, and said ground bus are connected to a power source, a signal source, and a ground source, respectively, under said passivation layer through openings in said passivation layer and wherein said power bus, said signal bus, said ground bus, and said gold bonding pads are formed with a same type of material.

67. The chip structure according to claim 66 wherein said openings in said passivation layer are greater than 0.1 micron in diameter.

68. A chip structure comprising:

a semiconductor substrate including semiconductor device structures formed in and on said substrate;

a plurality of layers of metal interconnection lines connecting to said semiconductor device structures;

a plurality of bonding pads formed in a topmost metal layer;

a passivation layer overlying said bonding pads wherein said passivation layer comprises a plurality of openings through which said bonding pads are exposed;

a plurality of wire bonding pads disposed on a first subset of said plurality of bonding pads wherein a surface layer of said wire bonding pads is gold; and

a plurality of solder pads disposed on a second subset of said plurality of bonding pads not covered by said wire bonding pads wherein a surface layer of said solder pads is copper or gold.

69. The chip structure according to claim 68 further comprising a plurality of gold bumps disposed on said wire bonding pads.

70. The chip structure according to claim 68 wherein said bonding pads comprise copper, aluminun, or an aluminum alloy.

71. The chip structure according to claim 68 wherein each of said wire bonding pads further comprises:

an adhesion/barrier layer directly overlying said bonding pad; and

a gold film layer disposed on said adhesion/barrier layer.

72. The chip structure according to claim 71 wherein said adhesion/barrier layer comprises a titanium-tungsten alloy, tantalum, tantalum nitride, or titanium nitride.

73. The chip structure according to claim 68 wherein each of said solder pads further comprises:

an adhesion layer; and

a seed layer for electroplating sputtered onto said adhesion layer.

74. The chip structure according to claim 73 wherein a material comprising said adhesion layer is titanium, chromium, a chromium-copper alloy, or a titanium-tungsten alloy or a combination of these materials.

75. The chip structure according to claim 73 wherein said seed layer for electroplating comprises copper.

76. The chip structure according to claim 73 wherein each of said solder pads further comprises a diffusion barrier layer disposed on said seed layer for electroplating.

77. The chip structure according to claim 76 wherein said diffusion barrier layer comprises nickel, copper, or a copper-nickel composite layer.

78. The chip structure according to claim 76 wherein each of said solder pads further comprises a solder wettable layer disposed on said diffusion barrier layer.

79. The chip structure according to claim 78 wherein said solder wettable layer comprises gold, copper, tin, a tin-lead alloy, or an unleaded solder material.

80. The chip structure according to claim 78 further comprising a plurality of solders disposed on said solder wettable layer.

81. The chip structure according to claim 78 further comprising a plurality of solder bumps disposed on said solder wettable layer.

82. The chip structure according to claim 81 wherein said solder bumps comprise a tin-lead alloy, a tin-silver alloy, or a tin-silver-copper alloy, or any other unleaded solder material.

83. The chip structure according to claim 68 further comprising a post-passivation metal interconnect line overlying said passivation layer wherein said post-passivation metal interconnect line and said wire bonding pads comprise a same type of material.

84. The chip structure according to claim 83 wherein said post-passivation metal interconnect line comprises a power bus, a signal bus, and a ground bus.

85. A chip structure comprising:

a semiconductor substrate including semiconductor device structures formed in and on said substrate;

a plurality of layers of metal interconnection lines connecting to said semiconductor device structures;

a plurality of bonding pads formed in a topmost metal layer;

a passivation layer overlying said bonding pads wherein said passivation layer comprises a plurality of openings through which said bonding pads are exposed;

a plurality of wire bonding pads disposed on a first subset of said plurality of bonding pads wherein each of said wire bonding pads comprises an adhesion layer/copper/nickel/gold layer; and

a plurality of solder pads disposed on a second subset of said plurality of bonding pads not covered by said wire bonding pads wherein each of said solder pads comprises an adhesion layer/copper/nickel/gold layer.

86. The chip structure according to claim 85 wherein said adhesion layer is titanium, chromium, or a chromium-copper alloy.

87. The chip structure according to claim 85 wherein said bonding pads comprise copper, aluminum, or an aluminum alloy.

88. The chip structure according to claim 85 further comprising a plurality of solders disposed on said solder pads wherein said solders comprise a tin-lead alloy, a tin-silver alloy, or a tin-silver-copper alloy, or any other unleaded solder material.

89. The chip structure according to claim 85 further comprising a post-passivation metal interconnect line overlying said passivation layer wherein said post-passivation metal interconnect line and said wire bonding pads comprise a same type of material.

90. The chip structure according to claim 89 wherein said post-passivation metal interconnect line comprises a power bus, a signal bus, and a ground bus.

91. A chip structure comprising:

a semiconductor substrate including semiconductor device structures formed in and on said substrate;

a plurality of layers of metal interconnection lines connecting to said semiconductor device structures;

a plurality of bonding pads formed in a topmost metal layer;

a passivation layer overlying said bonding pads wherein said passivation layer comprises a plurality of openings through which said bonding pads are exposed;

a post-passivation metal interconnect structure disposed on said passivation layer and connected to a circuit underlying said passivation layer through said openings in said passivation layer to a first subset of said bonding pads;

a plurality of wire bonding pads disposed on a second subset of said plurality of bonding pads not connected to said interconnect structure wherein a surface layer of each of said wire bonding pads comprises a gold bump and wherein said metal interconnect structure and said wire bonding pads comprise a same material; and

a plurality of solder pads disposed on a third subset of said plurality of bonding pads not covered by said wire bonding pads and not connected to said interconnect structure wherein a surface layer of each of said solder pads comprises a solder bump.

92. The chip structure according to claim 91 wherein said post-passivation metal interconnect structure connects a part of a circuit under said passivation layer to other parts of said circuit under said passivation layer through said openings.

93. The chip structure according to claim 92 wherein said openings in said passivation layer are greater than 0.1 micron in diameter.

94. The chip structure according to claim 91 wherein said post-passivation metal interconnect structure further comprises a power bus, a signal bus, and a ground bus above said passivation layer wherein said power bus, said signal bus, and said ground bus are connected to a power source, a signal source, and a ground source, respectively, under said passivation layer through said openings in said passivation layer.

95. The chip structure according to claim 94 wherein said openings in said passivation layer are greater than 0.1 micron in diameter.

96. The chip structure according to claim 91 wherein said post-passivation metal interconnect structure further comprises a redistribution layer.

97. The chip structure according to claim 91 wherein each of said gold bumps is connected to an external circuit through a bonding wire and wherein each of said solder bumps is connected to said external circuit.

98. The chip structure according to claim 91 wherein said gold bumps are used as testing pads.

99. The chip structure according to claim 91 wherein each of said gold bumps has a thickness of between about 1 micron and 60 microns.

100. The chip structure according to claim 91 wherein each of said solder bumps has a thickness of between about 1 micron and 400 microns.

101. The chip structure according to claim 91 wherein said solder bumps comprise a tin-lead alloy, a tin-silver alloy, or a tin-silver-copper alloy, or any other unleaded solder material.

102. A chip structure comprising:

a semiconductor substrate including semiconductor device structures formed in and on said substrate;

a plurality of layers of metal interconnection lines connecting to said semiconductor device structures;

a plurality of metal pads formed in a topmost metal layer;

a passivation layer overlying said metal pads wherein said passivation layer comprises a plurality of openings through which said metal pads are exposed;

a post-passivation metal interconnect structure disposed on said passivation layer and connected to a circuit underlying said passivation layer through said openings in said passivation layer to said metal pads;

a plurality of bonding pads on a surface of said post-passivation metal interconnect structure;

a plurality of wire bonding pads disposed on a first subset of said plurality of bonding pads wherein a surface layer of each of said wire bonding pads is a gold bonding pad; and

a plurality of solder pads disposed on a second subset of said plurality of bonding pads not covered by said wire bonding pads.

103. The chip structure according to claim 102 wherein said post-passivation metal interconnect structure connects a part of a circuit under said passivation layer to other parts of said circuit under said passivation layer through said openings.

104. The chip structure according to claim 103 wherein said openings in said passivation layer are greater than 0.1 micron in diameter.

105. The chip structure according to claim 102 wherein said post-passivation metal interconnect structure further comprises a power bus, a signal bus, and a ground bus above said passivation layer wherein said power bus, said signal bus, and said ground bus are connected to a power source, a signal source, and a ground source, respectively, under said passivation layer through said openings in said passivation layer.

106. The chip structure according to claim 105 wherein said openings in said passivation layer are greater than 0.1 micron in diameter.

107. The chip structure according to claim 102 wherein said post-passivation metal interconnect structure further comprises a redistribution layer.

108. The chip structure according to claim 102 wherein each of said gold bonding pads is connected to an external circuit through a bonding wire.

109. The chip structure according to claim 102 wherein said gold bonding pads are used as testing pads.

110. The chip structure according to claim 102 wherein each of said gold bonding pads has a thickness of between about 0.1 micron and 3.0 microns.

111. The chip structure according to claim 102 wherein a surface layer of each of said solder pads comprises a solder bump.

112. The chip structure according to claim 102 wherein said solder pads comprise gold.

113. The chip structure according to claim 112 wherein each of said solder bumps has a thickness of between about 1 micron and 400 microns.

114. The chip structure according to claim 112 wherein said solder bumps comprise a tin-lead alloy, a tin-silver alloy, or a tin-silver-copper alloy, or any other unleaded solder material.

115. The chip structure according to claim 102 further comprising a non-reflowed solder bump on a surface of each of a plurality of said solder pads.

116. An electrical connecting structure of a chip and an external circuit comprising:

a semiconductor substrate including semiconductor device structures formed in and on said substrate;

a plurality of layers of metal interconnection lines connecting to said semiconductor device structures;

a plurality of bonding pads formed in a topmost metal layer;

a passivation layer overlying said bonding pads wherein said passivation layer comprises a plurality of openings through which said bonding pads are exposed;

a plurality of wire bonding pads disposed on a first subset of said plurality of bonding pads exposed through said openings wherein a surface layer of each of said wire bonding pads comprises gold;

a plurality of bond wires electrically connecting between said wire bonding pads and said external circuit;

a plurality of solder pads disposed on a second subset of said plurality of bonding pads not covered by said wire bonding pads; and

a plurality of solders disposed on said solder pads to electrically connect to said external circuit.

117. The structure according to claim 116 wherein a surface layer of said wire bonding pads comprises a gold bump.

118. The structure according to claim 117 wherein said gold bump has a thickness of between about 1 micron and 60 microns.

119. The structure according to claim 117 wherein said bonding wires are connected to a region under said gold bumps wherein said region comprises an active device, a passive device, or a metal interconnect.

120. The structure according to claim 116 wherein a surface layer of said wire bonding pads comprises a gold bonding pad.

121. The structure according to claim 120 wherein said gold bonding pad has a thickness of between about 0.005 micron and 5.0 microns.

122. The structure according to claim 116 wherein a surface layer of said solder pads comprises a solder bump.

123. The structure according to claim 122 wherein said solder bumps have a thickness of between about 1 micron and 400 microns.

124. The structure according to claim 122 wherein said solder bumps comprise a tin-lead alloy, a tin-silver alloy, or a tin-silver-copper alloy, or any other unleaded solder material.

125. The structure according to claim 116 wherein each of said wire bonding pads and each of said solder pads comprises an adhesion layer/copper/nickel/gold layer.

126. The structure according to claim 125 wherein said adhesion layer is titanium, chromium, or a chromium-copper alloy.

127. The structure according to claim 116 wherein said bonding pads comprise copper, aluminum, or an aluminum alloy.

128. The structure according to claim 116 wherein a material used in forming said solders comprises a tin-lead alloy, a tin-silver alloy, or a tin-silver-copper alloy, or any other unleaded solder material.

129. The structure according to claim 116 wherein said passivation layer further comprises a metal interconnect thereover and wherein said metal interconnect and said wire bonding pads are a same type of material.

130. The structure according to claim 129 wherein said metal interconnect comprises a power bus, a signal bus, and a ground bus.

131. A chip fabrication process comprising:

providing a substrate comprising a plurality of semiconductor device structures and overlying layers of interconnection lines wherein a plurality of bonding pads are formed in a topmost metal layer and wherein a passivation layer overlies said bonding pads wherein said passivation layer comprises a plurality of openings through which said bonding pads are exposed;

forming a plurality of wire or TAB bonding pads disposed on a first subset of said plurality of bonding pads wherein a surface layer of said wire or TAB bonding pads is gold; and

forming a plurality of solder pads disposed on a second subset of said plurality of bonding pads not covered by said wire or TAB bonding pads.

132. The process according to claim 131 wherein said forming said wire or TAB bonding pads comprises:

forming an adhesion/barrier layer overlying said passivation layer and on said bonding pads;

forming a gold film layer on said adhesion/barrier layer;

forming a mask layer on said gold film layer;

forming a plurality of mask openings in said mask layer wherein said mask openings are disposed above said first subset of said bonding pads and wherein said mask openings expose said gold film layer;

forming a plurality of gold bumps on said gold film layer exposed by said mask openings;

thereafter removing said mask layer;

removing said gold film layer not underlying said gold bumps; and

removing said adhesion layer not underlying said gold bumps.

133. The process according to claim 132 wherein said adhesion/barrier layer comprises a titanium tungsten alloy, tantalum, tantalum nitride, or titanium nitride.

134. The process according to claim 132 wherein said adhesion/barrier layer is formed by a sputtering process.

135. The process according to claim 132 wherein said gold bumps are formed by electroplating.

136. The process according to claim 132 wherein said removing said adhesion/barrier layer is by a wet etching method wherein said wet etching method uses a H₂O₂-containing liquid.

137. The process according to claim 132 further comprising forming a redistribution layer overlying said passivation layer wherein said redistribution layer redistributes original positions of said bonding pads to specific other positions and wherein said gold bumps and said redistribution layer are formed of a same material and by the same process.

138. The process according to claim 131 wherein said forming said wire or TAB bonding pads comprises:

forming an adhesion/barrier layer overlying said passivation layer and on said bonding pads;

forming a gold film layer on said adhesion/barrier layer;

forming a mask layer on said gold film layer;

exposing and developing said mask layer to expose said gold film layer not directly above said first subset of said bonding pads;

removing said gold film layer and said adhesion layer not covered by said mask layer to leave said gold film layer and said adhesion layer covered by said mask layer to form gold bonding pads; and

thereafter removing said mask layer.

139. The process according to claim 138 wherein said adhesion/barrier layer comprises a titanium tungsten alloy, tantalum, tantalum nitride, or titanium nitride.

140. The process according to claim 138 wherein said adhesion/barrier layer is formed by a sputtering process.

141. The process according to claim 138 wherein said gold film layer is formed by a sputtering or electroplating process.

142. The process according to claim 138 wherein said removing said adhesion/barrier layer is by a wet etching method wherein said wet etching method uses a H₂O₂-containing liquid.

143. The process according to claim 138 wherein when forming said gold bonding pads, a metal interconnect is also formed of the same material and by the same process.

144. The process according to claim 143 wherein said metal interconnect connects a part of a circuit under said passivation layer to another part of said circuit under said passivation layer through said openings in said passivation layer.

145. The process according to claim 144 wherein said openings in said passivation layer are greater than 0.1 micron.

146. The process according to claim 138 wherein when forming said gold bonding pads, a power bus, a signal bus, and a ground bus are also formed to connect a power source, a signal source, and a ground source, respectively, through openings in said passivation layer.

147. The process according to claim 146 wherein said openings in said passivation layer are greater than 0.1 micron.

148. The process according to claim 131 wherein said forming said solder pads comprises:

forming an adhesion layer over said passivation layer, said bonding pads, and said wire bonding pads;

forming a seed layer for electroplating on said adhesion layer;

forming a mask layer on said seed layer for electroplating;

forming a plurality of mask openings in said mask layer wherein said mask openings are located over said second subset of bonding pad not covered by said wire or TAB bonding pads and wherein said openings expose said seed layer for electroplating;

forming a diffusion barrier layer over said seed layer for electroplating exposed by said mask openings;

forming a solder layer on said diffusion barrier layer;

thereafter removing said mask layer; and

thereafter removing said seed layer for electroplating and said adhesion layer that are not covered by said solder layer.

149. The process according to claim 148 wherein said adhesion layer comprises titanium, chromium, or a chromium-copper alloy.

150. The process according to claim 148 wherein said adhesion layer is formed by a sputtering process.

151. The process according to claim 148 wherein said seed layer for electroplating comprises copper.

152. The process according to claim 148 wherein said seed layer for electroplating is formed by a sputtering process.

153. The process according to claim 148 wherein said diffusion barrier layer is nickel, copper, tin, a tin-copper composite layer, or a copper-nickel composite layer.

154. The process according to claim 148 wherein said solder layer comprises a tin-lead alloy, a tin-silver alloy, or a tin-silver-copper alloy, or any other unleaded solder material.

155. The process according to claim 148 wherein said solder layer is formed by an electroplating method.

156. The process according to claim 148 wherein said solder layer is formed by a printing method.

157. The process according to claim 148 further comprising forming a solder-wettable layer on said diffusion barrier layer prior to forming said solder layer.

158. The process according to claim 157 wherein said solder-wettable layer comprises gold, copper, tin, a tin-lead alloy, or an unleaded solder material.

159. The process according to claim 148 wherein said solder layer comprises unreflowed solder.

160. The process according to claim 148 further comprising reflowing said solder layer to form solder bumps.

161. The process according to claim 131 wherein said forming said solder pads comprises:

forming an underbump metallization (UBM) layer over said passivation layer, said bonding pads, and said wire bonding pads;

forming a mask layer on said UBM layer;

forming a plurality of mask openings in said mask layer wherein said mask openings are located over said second subset of bonding pads not covered by said wire or TAB bonding pads and wherein said openings expose said UBM layer;

forming a solder layer on said UBM layer;

thereafter removing said mask layer; and

thereafter removing said UBM layer not covered by said solder layer.

162. The process according to claim 161 further comprising reflowing said solder layer to form solder bumps.

163. The process according to claim 131 wherein said forming said wire or TAB bonding pads and said solder pads comprises:

depositing an adhesion layer overlying said passivation layer and said bonding pads;

depositing a copper layer overlying said adhesion layer;

depositing a nickel layer overlying said copper layer; and

depositing a gold layer overlying said nickel layer; and

patterning said gold layer, said nickel layer, said copper layer, and said adhesion layer to form said wire or TAB bonding pads and said solder pads over said bonding pads.

164. The process according to claim 163 wherein said adhesion layer comprises titanium, chromium, or a copper-chromium alloy.

165. The process according to claim 131 further comprising forming connections from said wire or TAB bonding pads and said solder pads wherein said connections comprise wire bonds, TAB leads, solder bumps, or unreflowed solder.

166. A chip fabrication process comprising:

providing a substrate comprising a plurality of semiconductor device structures and overlying layers of interconnection lines wherein a plurality of bonding pads are formed in a topmost metal layer and wherein a passivation layer overlies said bonding pads wherein said passivation layer comprises a plurality of openings through which said bonding pads are exposed;

forming a plurality of wire or TAB bonding pads disposed on a first subset of said plurality of bonding pads wherein a surface layer of said wire or TAB bonding pads comprises gold;

forming a plurality of solder pads disposed on a second subset of said plurality of bonding pads not covered by said wire or TAB bonding pads; and

dicing said substrate to form a plurality of chips.

167. The process according to claim 166 wherein said wire or TAB bonding pads are formed by a sputtering method.

168. The process according to claim 166 wherein said solder pads are formed by sputtering or electroplating.

169. The process according to claim 166 wherein said forming said wire or TAB bonding pads comprises:

forming a patterned adhesion/barrier layer on said first subset of said bonding pads; and

forming a gold film layer on said adhesion/barrier layer.

170. The process according to claim 169 wherein said adhesion/barrier layer comprises a titanium-tungsten alloy, tantalum, tantalum nitride, or titanium nitride.

171. The process according to claim 166 further comprising forming gold bumps on said wire or TAB bonding pads.

172. The process according to claim 166 wherein said forming said solder pads comprises:

forming an adhesion layer on said substrate surface covering said wire or TAB bonding pads and said bonding pads;

forming a mask layer on said adhesion layer having a plurality of mask openings located above said second subset of bonding pads;

forming an electroplating layer on said adhesion layer exposed within said mask openings;

therafter removing said mask layer; and

removing said adhesion layer not covered by said electroplating layer.

173. The process according to claim 172 wherein said adhesion layer comprises titanium, chromium, or a chromium-copper alloy, or a combination of these materials.

174. The process according to claim 172 wherein said electroplating layer comprises copper.

175. The process according to claim 172 further comprising forming a diffusion barrier layer overlying said electroplating layer.

176. The process according to claim 175 wherein said diffusion barrier layer comprises nickel, copper, tin, a tin-copper composite layer, or a copper-nickel composite layer.

177. The process according to claim 175 further comprising forming a solder-wettable layer on said diffusion barrier layer.

178. The process according to claim 177 wherein said solder-wettable layer comprises gold, copper, tin, a tin-lead alloy, or an unleaded solder material.

179. The process according to claim 172 further comprising forming a solder layer on said solder pads.

180. The process according to claim 179 further comprising reflowing said solder layer to form solder bumps.

181. The process according to claim 166 further comprising forming a metal interconnect on said passivation layer during said forming of said wire bonding pads wherein said metal interconnect comprises a same material as said wire or TAB bonding pads.

182. A chip structure comprising:

a substrate comprising a plurality of bonding pads and a passivation layer overlying said bonding pads wherein said passivation layer comprises a plurality of openings through which said bonding pads are exposed;

a plurality of TAB bonding pads disposed on a first subset of said plurality of bonding pads exposed through said openings and further comprising a gold bump on each of said TAB bonding pads; and

a plurality of solder pads disposed on a second subset of said plurality of bonding pads not covered by said TAB bonding pads.

183. The chip structure according to claim 182 further comprising:

semiconductor device structures formed in and on said substrate; and

a plurality of layers of metal interconnection lines connecting to said semiconductor device structures wherein said bonding pads are formed in a topmost metal layer.

184. The chip structure according to claim 182 wherein said gold bumps are connected to one or more external circuits though a plurality of TAB leads.

185. The chip structure according to claim 182 wherein each of said gold bumps has a thickness of between about 1 micron and 60 microns.

186. The chip structure according to claim 182 wherein each of said TAB bonding pads further comprises an adhesion/barrier layer underlying said gold bump and directly overlying said bonding pad.

187. The chip structure according to claim 186 wherein said adhesion layer comprises a titanium-tungsten alloy, tantalum, tantalum nitride, or titanium nitride.

188. The chip structure according to claim 182 wherein a thickness of said bonding pads is between about 0.1 micron and 3 microns.

189. The chip structure according to claim 182 wherein a surface layer of each of said solder pads comprises a solder bump.

190. The chip structure according to claim 189 wherein said solder bumps comprise a tin-lead alloy, a tin-silver alloy, a tin-silver-copper alloy, or any other unleaded solder material.

191. The chip structure according to claim 189 wherein said solder bumps are connected to an external circuit.

192. The chip structure according to claim 189 wherein each of said solder pads comprises an underbump metallization (UBM) layer and an overlying solder bump.

193. The chip structure according to claim 189 wherein each of said solder pads comprises:

an adhesion layer; and

a seed layer for electroplating sputtered onto said adhesion layer.

194. The chip structure according to claim 193 wherein a material comprising said adhesion layer is titanium, chromium, a chromium-copper alloy, or a titanium-tungsten alloy, or a combination of these materials.

195. The chip structure according to claim 193 wherein said seed layer for electroplating comprises copper.

196. The chip structure according to claim 193 wherein each of said solder pads further comprises a diffusion barrier layer disposed on said seed layer for electroplating.

197. The chip structure according to claim 196 wherein said diffusion barrier layer comprises nickel, tin, copper, a tin-copper composite layer, or a copper-nickel composite layer.

198. The chip structure according to claim 196 wherein each of said solder pads further comprises a solder wettable layer disposed on said diffusion barrier layer.

199. The chip structure according to claim 198 wherein said solder wettable layer comprises gold, copper, tin, a tin-lead alloy, or an unleaded solder material.

200. The chip structure according to claim 198 further comprising a plurality of solders disposed on said solder-wettable layer.

201. The chip structure according to claim 198 further comprising a plurality of solder bumps formed on said solder-wettable layer.

202. The chip structure according to claim 201 wherein said solder bumps comprise a tin-lead alloy, a tin-silver alloy, or a tin-silver-copper alloy or any other unleaded solder material.

203. The chip structure according to claim 182 wherein said bonding pads comprise copper, aluminum, or an aluminum alloy.