Switch circuit and method of switching radio frequency signals

• US 20050017789A1
• Filed: 08/18/2004
• Published: 01/27/2005
• Est. Priority Date: 10/10/2001
• Status: Active Grant

• Current Assignee: pSemi Corporation (Murata Manufacturing Co Limited)
• Original Assignee: James S. Cable, Mark L. Burgener
• Inventors: Burgener, Mark L., Cable, James S.
• Granted Patent: US 7,123,898 B2
• Time in Patent Office: Days
• US Class Current: 327/436
• CPC Class Codes: H01P 1/15 by semiconductor devices
• CPC Class Codes: H03K 17/063 in field-effect transistor switches
• CPC Class Codes: H03K 17/102 in field-effect transistor switches
• CPC Class Codes: H03K 17/6871 the output circuit comprising more than one controlled field-effect transistor
• CPC Class Codes: H03K 17/693 Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors logic circuits H03K19/00; code converters H03M5/00, H03M7/00
• CPC Class Codes: H03K 19/018521 of complementary type, e.g. CMOS
• CPC Class Codes: H03K 19/0944 using MOSFET or insulated gate field-effect transistors, i.e. IGFETH03K19/096 takes precedence
• CPC Class Codes: H03K 2017/0803 against radiation hardening
• CPC Class Codes: H04B 1/40 Circuits

Abstract

A novel RF buffer circuit adapted for use with an RF switch circuit and method for switching RF signals is described. The RF switch circuit is fabricated in a silicon-on-insulator (SOI) technology. The RF switch includes pairs of switching and shunting transistor groupings used to alternatively couple RF input signals to a common RF node. The switching and shunting transistor grouping pairs are controlled by a switching control voltage (SW) and its inverse (SW_). The switching and shunting transistor groupings comprise one or more MOSFET transistors connected together in a “stacked” or serial configuration. The stacking of transistor grouping devices, and associated gate resistors, increase the breakdown voltage across the series connected switch transistors and operate to improve RF switch compression. A fully integrated RF switch is described including digital control logic and a negative voltage generator integrated together with the RF switch elements. In one embodiment, the fully integrated RF switch includes a built-in oscillator, a charge pump circuit, CMOS logic circuitry, level-shifting and voltage divider circuits, and an RF buffer circuit. Several embodiments of the charge pump, level shifting, voltage divider, and RF buffer circuits are described. The inventive RF switch provides improvements in insertion loss, switch isolation, and switch compression.

Claims

1. An RF buffer circuit adapted for use with an RF switch circuit, the RF buffer circuit comprising a two-stage circuit comprising a first-stage level-shifting circuit and a second stage RF buffer circuit, and wherein the first stage level-shifting circuit comprises a level-shifting circuit, and wherein the second stage RF buffer circuit comprises a second plurality of differential inverters, wherein the second plurality of differential inverters each have a first differential input, a second differential input, a logic input and a logic output, wherein the second stage RF buffer circuit further comprises:

(a) a first RF buffer inverter group comprising three differential inverters, wherein the logic inputs of a first and second inverters of the first RF buffer inverter group are coupled to the first output signal (out) output by the level-shifting circuit, the logic output of the first inverter of the first RF buffer inverter group is coupled to a first differential input of an output inverter of the first RF buffer inverter group, the logic output of the second inverter of the first RF buffer inverter group is coupled to a second differential input of the output inverter of the first RF buffer inverter group, and wherein the output inverter of the first RF buffer inverter group outputs a first output signal (OUT); and

(b) a second RF buffer inverter group comprising three differential inverters, wherein the logic inputs of a first and second inverters of the second RF buffer inverter group are coupled to the second output signal (out_) output by the level-shifting circuit, the logic output of the first inverter of the second RF buffer inverter group is coupled to a first differential input of an output inverter of the second RF buffer inverter group, the logic output of the second inverter of the second RF buffer inverter group is coupled to a second differential input of the output inverter of the second RF buffer inverter group, and wherein the output inverter of the second RF buffer inverter group outputs a second output signal (OUT_).