Charge pump circuit capable of completely cutting off parasitic transistors

• US 20050017792A1
• Filed: 06/28/2004
• Published: 01/27/2005
• Est. Priority Date: 07/23/2003
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Inventors: Kawagoshi, Hirokazu
• Granted Patent: US 7,084,697 B2
• Time in Patent Office: Days
• US Class Current: 327/536
• CPC Class Codes: H02M 3/073 Charge pumps of the Schenkel-type
• CPC Class Codes: H02M 3/078 with means for reducing the back bias effect, i.e. the effect which causes the threshold voltage of transistors to increase as more stages are added to the converters
• CPC Class Codes: H03K 2217/0018 Special modifications or use of the back gate voltage of a FET

Abstract

In a charge pump circuit including a first charging switching element connected between an input voltage receiving terminal (IVRT) and a first terminal of a step-up capacitor, a second charging switching element connected between a second terminal of the step-up capacitor and a power supply terminal, a first discharging switching element connected between the IVRT and the second terminal of the step-up capacitor, and a second discharging switching element (DSE2) connected between the first terminal of the step-up capacitor and an output terminal, a first switch circuit is connected between the IVRT and a back gate of the first charging switching element and between the first terminal of the step-up capacitor and the back gate of the first charging switching element. A second switch circuit is connected between the first terminal of the step-up capacitor and back gate of DSE2 and between the output terminal and back gate of DSE2.

Claims

1. A charge pump circuit comprising:

an input voltage receiving terminal;

a power supply terminal whose voltage is lower than that of said input voltage receiving terminal;

an output terminal;

a step-up capacitor having first and second terminals;

a first charging switching element formed by a first P-channel MOS transistor connected between said input voltage receiving terminal and the first terminal of said step-up capacitor;

a second charging switching element connected between the second terminal of said step-up capacitor and said power supply terminal;

a first discharging switching element connected between said input voltage receiving terminal and the second terminal of said step-up capacitor;

a second discharging switching element formed by a second P-channel MOS transistor connected between the first terminal of said step-up capacitor and said output terminal;

a first switch circuit connected between said input voltage receiving terminal and a back gate of said first P-channel MOS transistor and between the first terminal of said step-up capacitor and the back gate of said first P-channel MOS transistor; and

a second switch circuit connected between the first terminal of said step-up capacitor and a back gate of said second P-channel MOS transistor and between said output terminal and the back gate of said second P-channel MOS transistor,

wherein, when said first and second charging switching elements are turned ON, said first switch electrically connects the back gate of said first P-channel MOS transistor to said input voltage receiving terminal, and said second switch circuit electrically connects the back gate of said second P-channel MOS transistor to said output terminal, and

wherein, when said first and second discharging switching elements are turned ON, said first switch electrically connects the back gate of said first P-channel MOS transistor to the first terminal of said step-up capacitor, and said second switch circuit electrically connects the back gate of said second P-channel MOS transistor to the first terminal of said step-up capacitor.

2. The charge pump circuit as set forth in claim 1, wherein said first switch circuit comprises:

a third P-channel MOS transistor connected between said input voltage receiving terminal and the back gate of said first P-channel MOS transistor; and

a fourth P-channel MOS transistor connected between the first terminal of said step-up capacitor and the back gate of said first P-channel MOS transistor, and

wherein said second switch circuit comprises;

a fifth P-channel MOS transistor connected between the first terminal of said step-up capacitor and the back gate of said second P-channel MOS transistor; and

a sixth P-channel MOS transistor connected between said output terminal and the back gate of said second P-channel MOS transistor,

said third and sixth P-channel MOS transistors being turned ON when said first and second charging switching elements are turned ON,

said fourth and fifth P-channel MOS transistors being turned ON when said first and second discharging switching elements are turned ON.

3. The charge pump circuit as set forth in claim 1, further comprising a logic circuit which compares a voltage at the first terminal of said step-up capacitor with an output voltage at said output voltage to control said second switch circuit in accordance with whether or not said output voltage is lower than the voltage at the first terminal of said step-up capacitor, when said first and second charging elements are turned ON.

4. The charge pump circuit as set forth in claim 3, wherein said logic circuit operates said second switch circuit so that said second switch circuit electrically connects the back gate of said second P-channel MOS transistor to the first terminal of said step-up capacitor when said output voltage is lower than the voltage at the first terminal of said step-up capacitor, and said second switch circuit electrically connects the back gate of said second P-channel MOS transistor to said output terminal when said output voltage is not lower than the voltage at the first terminal of said step-up capacitor.

5. The charge pump circuit as set forth in claim 2, further comprising a logic circuit which compares a voltage at the first terminal of said step-up capacitor with an output voltage at said output voltage to control said fifth and sixth P-channel MOS transistors in accordance with whether or not said output voltage is lower than the voltage at the first terminal of said step-up capacitor, when said first and second charging elements are turned ON.

6. The charge pump circuit as set forth in claim 5, wherein said logic circuit turns ON said fifth P-channel MOS transistor when said output voltage is lower than the voltage at the first terminal of said step-up capacitor and turns ON said sixth P-channel MOS transistor when said output voltage is not lower than the voltage at the first terminal of said step-up capacitor.

7. The charge pump-circuit as set forth in claim 1, wherein said second charging switching element comprises an N-channel MOS transistor, and said first discharging switching element comprises a seventh P-channel MOS transistor.

8. The charge pump circuit as set forth in claim 1, wherein said power supply terminal comprises a ground terminal.

9. A charge pump circuit comprising:

an input voltage receiving terminal;

a power supply terminal whose voltage is lower than that of said input voltage receiving terminal;

an output terminal;

a step-up capacitor having first and second terminals;

a first charging switching element formed by a first P-channel MOS transistor connected between said input voltage receiving terminal and the first terminal of said step-up capacitor;

a second charging switching element connected between the second terminal of said step-up capacitor and said power supply terminal;

a first discharging switching element connected between said input voltage receiving terminal and the second terminal of said step-up capacitor;

a second discharging switching element formed by a second P-channel MOS transistor connected between the first terminal of said step-up capacitor and said output terminal;

a first switch circuit connected between said input voltage receiving terminal and a back gate of said first P-channel MOS transistor and between the first terminal of said step-up capacitor and the back gate of said first P-channel MOS transistor; and

a second switch circuit connected between the first terminal of said step-up capacitor and a back gate of said second P-channel MOS transistor and between said output terminal and the back gate of said second P-channel MOS transistor,

said first and second charging switching elements being turned ON by a first state of a clock signal,

said first and second discharging switching element being turned ON by a second state of said clock signal,

wherein, when said clock signal indicates said first state, said first switch circuit electrically connects the back gate of said first P-channel MOS transistor to said input voltage receiving terminal and said second switch circuit electrically connects the back gate of said second P-channel MOS transistor to said output terminal, and

wherein, when said clock signal indicates said second state, said first switch circuit electrically connects the back gate of said first P-channel MOS transistor to the first terminal of said step-up capacitor and said second switch circuit electrically connects the back gate of said second P-channel MOS transistor to the first terminal of said step-up capacitor.

10. The charge pump circuit as set forth in claim 9, wherein said first switch circuit comprises:

a third P-channel MOS transistor connected between said input voltage receiving terminal and the back gate of said first P-channel MOS transistor; and

a fourth P-channel MOS transistor connected between the first terminal of said step-up capacitor and the back gate of said first P-channel MOS transistor, and

wherein said second switch circuit comprises;

a fifth P-channel MOS transistor connected between the first terminal of said step-up capacitor and the back gate of said second P-channel MOS transistor; and

a sixth P-channel MOS transistor connected between said output terminal and the back gate of said second P-channel MOS transistor,

said third and sixth P-channel MOS transistors being turned ON by said first state of said clock signal,

said fourth and fifth P-channel MOS transistors being turned ON by said second state of said clock signal.

11. The charge pump circuit as set forth in claim 9, further comprising a logic circuit which compares a voltage at the first terminal of said step-up capacitor with an output voltage at said output voltage to control said second switch circuit in accordance with whether or not said output voltage is lower than the voltage at the first terminal of said step-up capacitor, when said first and second charging elements are turned ON.

12. The charge pump circuit as set forth in claim 11, wherein said logic circuit operates said second switch circuit so that said second switch circuit electrically connects the back gate of said second P-channel MOS transistor to the first terminal of said step-up capacitor when said output voltage is lower than the voltage at the first terminal of said step-up capacitor and said second switch circuit electrically connects the back gate of said second P-channel MOS transistor to said output terminal when said output voltage is not lower than the voltage at the first terminal of said step-up capacitor.

13. The charge pump circuit as set forth in claim 11, wherein said logic circuit comprises:

a comparator which compares the voltage at the first terminal of said step-up capacitor with said output voltage;

a NAND circuit which receives an output signal of said comparator and said clock signal; and

an inverter connected to said NAND circuit,

said second switch circuit being controlled by an output signal of said inverter and an output signal of said NAND circuit.

14. The charge pump circuit as set forth in claim 11, wherein said logic circuit comprises:

a comparator which compares the voltage at the first terminal of said step-up capacitor with said output voltage;

an OR circuit which receives an output signal of said comparator and an inverted signal of said clock signal; and

an inverter connected to said OR circuit,

said second switch circuit being controlled by an output signal of said inverter and an output signal of said OR circuit.

15. The charging pump circuit as set forth in claim 9, further comprising a logic circuit which compares a voltage at the first terminal of said step-up capacitor with an output voltage at said output voltage to control said fifth and sixth P-channel MOS transistors in accordance with whether or not said output voltage is lower than the voltage at the first terminal of said step-up capacitor, when said clock signal indicates said first state.

16. The charge pump circuit as set forth in claim 15, wherein said logic circuit turns ON said fifth P-channel MOS transistor when said output voltage is lower than the voltage at the first terminal of said step-up capacitor and turns ON said sixth P-channel MOS transistor when said output voltage is not lower than the voltage at the first terminal of said step-up capacitor.

17. The charge pump circuit as set forth in claim 15, wherein said logic circuit comprises:

a comparator which compares the voltage at the first terminal of said step-up capacitor with said output voltage;

a NAND circuit which receives an output signal of said comparator and said clock signal; and

an inverter connected to said NAND circuit,

said fifth P-channel MOS transistor being controlled by an output signal of said inverter,

said sixth P-channel MOS transistor being controlled by an output signal of said NAND circuit.

18. The charge pump circuit as set forth in claim 15, wherein said logic circuit comprises:

a comparator which compares the voltage at the first terminal of said step-up capacitor with said output voltage;

an OR circuit which receives an output signal of said comparator and an inverted signal of said clock signal and

an inverter connected to said OR circuit,

said fifth P-channel MOS transistor being controlled by an output signal of said inverter,

said sixth P-channel MOS transistor being controlled by an output signal of said OR circuit.

19. The charge pump circuit as set forth in claim 9, wherein said second charging switching element comprises an N-channel MOS transistor, and said first discharging switching element comprises a seventh P-channel MOS transistor.

20. The charge pump circuit as set forth in claim 9, wherein said power supply terminal comprises a ground terminal.