Shift register and display device
First Claim
1. A shift register comprising:
- a plurality of bistable circuits connected in series, each of the bistable circuits having a first state and a second state and outputting a stage output signal of a logic level in accordance with the state of that bistable circuit, and all or some of the plurality of bistable circuits sequentially taking on the first state for a predetermined time each in accordance with a clock signal that is inputted from outside;
a start position setting circuit for keeping the bistable circuit at a start position, which is the bistable circuit specified by a start position instruction signal that is inputted from outside, in the first state; and
a reset circuit for setting the bistable circuits other than the bistable circuit at the start position to the second state, after the bistable circuit at an end position, which is the bistable circuit specified by an end position instruction signal that is inputted from outside, has been set to the first state;
wherein, when the bistable circuit at the start position is kept at the first state, the bistable circuits from the start position to the end position are sequentially set to the first state for the predetermined time each in accordance with the clock signal.
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Accused Products
Abstract
A display device is provided with a shift register having a plurality of bistable circuits, each of the bistable circuits being connected to a corresponding scanning line. An RS flip-flop circuit provided in each of the bistable circuits functions as a memory portion for discriminating a start position of a display region for partial display. When partial display is carried out, first, only the RS flip-flop circuit corresponding to the start position of the display region is put into the set state, that is, only the bistable circuit corresponding to the start position of the display region is put into the set state. Moreover, the scanning lines that are connected to the bistable circuits from the start position to the end position are driven sequentially. During this, only the bistable circuit corresponding to the start position is kept in the set state, and the other bistable circuits are kept in the reset state.
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Citations
9 Claims
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1. A shift register comprising:
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a plurality of bistable circuits connected in series, each of the bistable circuits having a first state and a second state and outputting a stage output signal of a logic level in accordance with the state of that bistable circuit, and all or some of the plurality of bistable circuits sequentially taking on the first state for a predetermined time each in accordance with a clock signal that is inputted from outside;
a start position setting circuit for keeping the bistable circuit at a start position, which is the bistable circuit specified by a start position instruction signal that is inputted from outside, in the first state; and
a reset circuit for setting the bistable circuits other than the bistable circuit at the start position to the second state, after the bistable circuit at an end position, which is the bistable circuit specified by an end position instruction signal that is inputted from outside, has been set to the first state;
wherein, when the bistable circuit at the start position is kept at the first state, the bistable circuits from the start position to the end position are sequentially set to the first state for the predetermined time each in accordance with the clock signal. - View Dependent Claims (2, 3, 4)
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5. A display device comprising a scanning line driving circuit for driving a plurality of scanning lines and a signal line driving circuit for driving a plurality of signal lines, the display device having a partial display function in which a portion of a display screen serves as a display region;
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at least one of the scanning line driving circuit and the signal line driving circuit comprising a shift register; and
the shift register comprising;
a plurality of bistable circuits connected in series, each of the bistable circuits having a first state and a second state and outputting a stage output signal of a logic level in accordance with the state of that bistable circuit, and all or some of the plurality of bistable circuits sequentially taking on the first state for a predetermined time each in accordance with a clock signal that is inputted into the shift register from outside the shift register;
a start position setting circuit for keeping the bistable circuit at a start position, which is the bistable circuit specified by a start position instruction signal that is inputted from outside, in the first state; and
a reset circuit for setting the bistable circuits other than the bistable circuit at the start position to the second state, after the bistable circuit at an end position, which is the bistable circuit specified by an end position instruction signal that is inputted into the shift register from outside the shift register, has been set to the first state;
wherein, when the bistable circuit at the start position is kept at the first state, the bistable circuits from the start position to the end position are sequentially set to the first state for the predetermined time each in accordance with the clock signal. - View Dependent Claims (6, 7, 8, 9)
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Specification