ARRANGEMENT OF INTEGRATED CIRCUITS IN A MEMORY MODULE

• US 20050018495A1
• Filed: 01/29/2004
• Published: 01/27/2005
• Est. Priority Date: 01/29/2004
• Status: Abandoned Application

• Current Assignee: Netlist, Inc.
• Original Assignee: Netlist, Inc.
• Inventors: Bhakta, Jayesh R., Gervasi, William M., Pauley, Robert S.
• Application Number:
  US10/769,469
• Publication Number:
  US 20050018495A1
• Time in Patent Office: Days
• US Class Current: 365/199
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: H05K 1/023 using auxiliary mounted passive components or auxiliary substances printed passive components H05K1/16
• CPC Class Codes: H05K 1/0231 Capacitors or dielectric substances
• CPC Class Codes: H05K 1/0233 Filters, inductors or a magnetic substance
• CPC Class Codes: H05K 1/0237 High frequency adaptations H05K1/0216 takes precedence
• CPC Class Codes: H05K 1/0246 Termination of transmission lines
• CPC Class Codes: H05K 1/0298 Multilayer circuits
• CPC Class Codes: H05K 1/181 associated with surface mounted components
• CPC Class Codes: H05K 1/185 Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit semiconductor chips encapsulated by interconnect and support structures H01L23/5389, H01L24/00
• CPC Class Codes: H05K 2201/09263 Meander
• CPC Class Codes: H05K 2201/09336 Signal conductors in same plane as power plane
• CPC Class Codes: H05K 2201/09409 Multiple rows of pads, lands, terminals or dummy patterns; Multiple rows of mounted components
• CPC Class Codes: H05K 2201/10022 Non-printed resistor
• CPC Class Codes: H05K 2201/1003 Non-printed inductor
• CPC Class Codes: H05K 2201/10689 Leaded Integrated Circuit [IC] package, e.g. dual-in-line [DIL]
• CPC Class Codes: H05K 2201/10734 Ball grid array [BGA]; Bump grid array
• CPC Class Codes: Y02P 70/50 Manufacturing or production processes characterised by the final manufactured product

Abstract

Abstract of the Disclosure

Integrated circuits utilizing standard commercial packaging are arranged on a printed circuit board to allow the production of one-Gigabyte, two-Gigabyte, and four-Gigabyte capacity memory modules. A first row of integrated circuits is oriented in an opposite orientation to a second row of integrated circuits. The integrated circuits in the first row on a first lateral portion of the printed circuit board and in the second row on the first lateral portion are connected to a first addressing register with two register integrated circuits. The integrated circuits in the first row on the second lateral portion and in the second row on the second lateral portion are connected to a second addressing register with two register integrated circuits. Each addressing register processes a non-contiguous subset of the bits in each data word.

Claims

1. A memory module comprising:

a printed circuit board comprising a first lateral portion and a second lateral portion;

a first plurality of memory integrated circuits identical to one another, the first plurality of memory integrated circuits positioned on the first lateral portion of the printed circuit board;

a second plurality of memory integrated circuits identical to one another and identical to the memory integrated circuits of the first plurality, the second plurality of memory integrated circuits positioned on the second lateral portion of the printed circuit board;

a first register integrated circuit coupled to the first plurality of memory integrated circuits;

a second register integrated circuit coupled to the first plurality of memory integrated circuits;

a third register integrated circuit coupled to the second plurality of memory integrated circuits; and

a fourth register integrated circuit coupled to the second plurality of memory integrated circuits.

2. The memory module of Claim 1, wherein the memory integrated circuits comprise DDR2 SDRAM integrated circuits.

3. A memory module comprising:

a generally planar printed circuit board comprising an edge, a common signal trace connector area along the edge, and a first side, the printed circuit board having a first lateral portion and a second lateral portion;

a first row of memory integrated circuits identical to one another, the first row positioned on the first side of the printed circuit board, the first row being in proximity to the common signal trace connector area, the integrated circuits of the first row having a first orientation direction, the first row having a first number of integrated circuits on the first lateral portion and a second number of integrated circuits on the second lateral portion, the first number larger than the second number;

a second row of memory integrated circuits identical to the integrated circuits of the first row, the second row positioned on the first side of the printed circuit board, the second row being located physically farther from the common signal trace connector than is the first row, the integrated circuits of the second row having a second orientation direction at a non-zero angle relative to the first orientation direction, the second row having a third number of integrated circuits on the first lateral portion and a fourth number of integrated circuits on the second lateral portion, the third number larger than the fourth number;

a first addressing register comprising two register integrated circuits, the first addressing register coupled to the integrated circuits of the first row on the first lateral portion and coupled to the integrated circuits of the second row on the first lateral portion; and

a second addressing register comprising two register integrated circuits, the second addressing register coupled to the integrated circuits of the first row on the second lateral portion and coupled to the integrated circuits of the second row on the second lateral portion.

4. The memory module of Claim 3, wherein the first row is substantially parallel to the edge.

5. The memory module of Claim 3, wherein the second row is substantially parallel to the edge.

6. The memory module of Claim 3, wherein the memory integrated circuits comprise Double Data Rate SDRAM integrated circuits.

7. The memory module of Claim 3, wherein the memory integrated circuits comprise DDR2 SDRAM integrated circuits.

8. The memory module of Claim 3, wherein the memory integrated circuits comprise ball-grid-array (BGA) SDRAM integrated circuits.

9. The memory module of Claim 3, wherein the memory integrated circuits comprise PC133 SDRAM integrated circuits.

10. The memory module of Claim 3, wherein the non-zero angle is approximately 180 degrees.

11. The memory module of Claim 3, wherein the first number equals the third number.

12. The memory module of Claim 3, wherein the second number equals the fourth number.

13. The memory module of Claim 3, wherein the first number is at least five.

14. The memory module of Claim 3, wherein the second number is at least four.

15. The memory module of Claim 3, wherein the memory module further comprises:

a first plurality of data lines electrically connecting data pins of the first row of integrated circuits to the common signal trace connector area; and

a second plurality of data lines electrically connecting data pins of the second row of integrated circuits to the common signal trace connector area, whereby lengths of corresponding data lines of the first plurality of data lines and the second plurality of data lines are substantially the same.

16. The memory module of Claim 3, wherein the first addressing register and the second addressing register access data bits of non-contiguous subsets of a data word.

17. The memory module of Claim 16, wherein:

the first addressing register accesses data bits 0 to 3, 8 to 11, 16 to 19, and 24 to 27; and

the second addressing register accesses data bits 4 to 7, 12 to 15, 20 to 23, and 28 to 31.

18. The memory module of Claim 3, wherein the memory module has a height of approximately one-and-one-half (1½

) inches and a width of approximately five-and-one-fourth (5¼

) inches.

19. The memory module of Claim 3, further comprising:

a third row of memory integrated circuits identical to the integrated circuits of the first row, the third row positioned on a second side of the printed circuit board, the third row being in proximity to the common signal trace connector area, the integrated circuits of the third row having a third orientation direction, the first row and the third row having the same number of integrated circuits on the first lateral portion and the first row and the third row having the same number of integrated circuits on the second lateral portion; and

a fourth row of memory integrated circuits identical to the integrated circuits of the first row, the fourth row positioned on the second side of the printed circuit board, the fourth row being located physically farther from the common signal trace connector than is the third row, the integrated circuits of the fourth row having a fourth orientation direction at a non-zero angle relative to the third orientation direction, the second row and the fourth row having the same number of integrated circuits on the first lateral portion and the second row and the fourth row having the same number of integrated circuits on the second lateral portion,

wherein the first addressing register is coupled to the integrated circuits of the third row on the first lateral half and to the integrated circuits of the fourth row on the first lateral half and the second addressing register is coupled to the integrated circuits of the third row on the second lateral half and to the integrated circuits of the fourth row on the second lateral half.

20. The memory module of Claim 19, wherein the third orientation direction is substantially the same as the first orientation direction, and the fourth orientation direction is substantially the same as the second orientation direction.

21. A memory module comprising:

a generally planar printed circuit board comprising an edge, a common signal trace connector area along the edge, and a first side, the printed circuit board having a first lateral portion and a second lateral portion;

a first row of memory integrated circuits identical to one another, the first row positioned on the first side of the printed circuit board, the first row being in proximity to the common signal trace connector area, the integrated circuits of the first row having a first orientation direction, the first row having a first number of integrated circuits on the first lateral portion and a second number of integrated circuits on the second lateral portion, the first number larger than the second number;

a second row of memory integrated circuits identical to the integrated circuits of the first row, the second row positioned on the first side of the printed circuit board, the second row being located physically farther from the common signal trace connector than is the first row, the integrated circuits of the second row having a second orientation direction at a non-zero angle relative to the first orientation direction, the second row having a third number of integrated circuits on the first lateral portion and a fourth number of integrated circuits on the second lateral portion, the third number larger than the fourth number;

a first addressing register comprising at least one register integrated circuit, the first addressing register coupled to the integrated circuits of the first row on the first lateral portion and coupled to the integrated circuits of the second row on the first lateral portion; and

a second addressing register comprising at least one register integrated circuit, the second addressing register coupled to the integrated circuits of the first row on the second lateral portion and coupled to the integrated circuits of the second row on the second lateral portion.

22. The memory module of Claim 21, wherein the first addressing register comprises at least two register integrated circuits.

23. The memory module of Claim 21, wherein the second addressing register comprises at least two register integrated circuits.

24. A one-Gigabyte capacity memory module comprising 36 integrated circuits of type 256-Megabit SDRAM organized as 64 Meg by 4 bits in a ball grid array (BGA) package, the memory module being approximately five-and-one-fourth inches wide by approximately one-and-one-half inches high, the integrated circuits arranged in two rows on each of two surfaces of a printed circuit board.

25. The memory module of Claim 24, wherein the integrated circuits are DDR2 SDRAM.

26. A two-Gigabyte capacity memory module comprising 36 integrated circuits of type 512-Megabit SDRAM organized as 128 Meg by 4 bits in a ball grid array (BGA) package, the memory module being approximately five-and-one-fourth inches wide by approximately one-and-one-half inches high, the integrated circuits arranged in two rows on each of two surfaces of a printed circuit board.

27. The memory module of Claim 26, wherein the integrated circuits are DDR2 SDRAM.

28. A four-Gigabyte capacity memory module comprising 36 integrated circuits of type 1024-Megabit SDRAM organized as 256 Meg by 4 bits in a ball grid array (BGA) package, the memory module being approximately five-and-one-fourth inches wide by approximately one-and-one-half inches high, the integrated circuits arranged in two rows on each of two surfaces of a printed circuit board.

29. The memory module of Claim 28, wherein the integrated circuits are DDR2 SDRAM.

30. A memory module comprising:

a printed circuit board having a plurality of signal lines;

a plurality of memory integrated circuit packages mounted on a first face of the printed circuit board, each memory integrated circuit package having a plurality of conductive contacts; and

a plurality of passive components electrically coupled to the plurality of conductive contacts and the plurality of signal lines, the plurality of passive components embedded within the printed circuit board.

31. The memory module of Claim 30, wherein the embedded passive components comprise embedded resistors.

32. The memory module of Claim 31, wherein the embedded resistors comprise series damping resistors positioned in proximity to corresponding conductive contacts of the memory integrated circuit packages.

33. The memory module of Claim 32, wherein the series damping resistors are positioned directly under the corresponding conductive contacts of the memory integrated circuit packages.

34. The memory module of Claim 31, wherein the embedded resistors comprise line damping resistors positioned in proximity to corresponding branching points of the signal lines.

35. The memory module of Claim 31, wherein the printed circuit board comprises an edge connector comprising a plurality of edge connections, and wherein the embedded resistors comprise line damping resistors positioned in proximity to corresponding edge connections of the edge connector.

36. The memory module of Claim 31, wherein the signal lines comprise differential signal path pairs, and wherein the embedded resistors comprise termination resistors positioned at an end of each signal path pair.

37. The memory module of Claim 36, wherein the embedded resistors further comprise termination resistors positioned at branches of the signal path pairs.

39. The memory module of Claim 31, wherein the embedded resistors comprise pull-up or pull-down resistors.

40. The memory module of Claim 31, wherein the embedded resistors comprises voltage dividers to create voltage levels not supplied to the memory module from a host system.

41. The memory module of Claim 30, wherein the embedded passive components comprise embedded capacitors.

42. The memory module of Claim 41, wherein the embedded capacitors comprise decoupling capacitors.

43. The memory module of Claim 41, wherein the embedded capacitors comprise load matching capacitors.

44. The memory module of Claim 41, wherein the embedded capacitors comprise capacitors adapted for signal quality shaping and filtering.

45. The memory module of Claim 41, wherein the embedded capacitors comprise capacitors adapted for voltage spike decoupling.

46. The memory module of Claim 41, wherein the embedded capacitors comprise capacitors adapted to match loading characteristics of selected signals.

47. The memory module of Claim 41, wherein the embedded capacitors comprise capacitors adapted to smooth out voltage spikes by providing short-term power.

48. The memory module of Claim 30, wherein the embedded passive components comprise embedded inductors.

49. The memory module of Claim 48, wherein the embedded inductors are adapted to filter low frequency noise from electrical signals.

50. The memory module of Claim 30, wherein the embedded passive components comprise embedded capacitors and an embedded inductor, the embedded capacitors coupled to the embedded inductor to provide an embedded flux capacitor.

51. The memory module of Claim 50, wherein the embedded flux capacitor is adapted to provide a bandpass filter for a selected frequency response range.

38. A four-Gigabyte capacity memory module comprising 36 integrated circuits of type 1-Gigabit SDRAM organized as 256 Meg by 4 bits in a Thin Small Outline Package (TSOP), the memory module having an approximate width of 5.25 inches and an approximate height of 2.05 inches.

52. A memory module comprising:

a printed circuit board comprising a first portion and a second portion;

a first plurality of memory integrated circuits identical to one another, the first plurality of memory integrated circuits positioned on the first portion of the printed circuit board;

a second plurality of memory integrated circuits identical to one another and identical to the memory integrated circuits of the first plurality, the second plurality of memory integrated circuits positioned on the second portion of the printed circuit board;

a first register integrated circuit coupled to the first plurality of memory integrated circuits;

a second register integrated circuit coupled to the first plurality of memory integrated circuits;

a third register integrated circuit coupled to the second plurality of memory integrated circuits; and

a fourth register integrated circuit coupled to the second plurality of memory integrated circuits.

53. The memory module of Claim 52, wherein the memory integrated circuits comprise DDR2 SDRAM integrated circuits.

54. The memory module of Claim 52, wherein the memory integrated circuits comprise Double Data Rate SDRAM integrated circuits.

55. The memory module of Claim 52, wherein the memory integrated circuits comprise ball-grid-array (BGA) SDRAM integrated circuits.

56. The memory module of Claim 52, wherein the memory integrated circuits comprise PC133 SDRAM integrated circuits.