Dynamic memory word line driver scheme

• US 20050018523A1
• Filed: 03/02/2004
• Published: 01/27/2005
• Est. Priority Date: 04/06/1990
• Status: Active Grant

• Current Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Original Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Inventors: Lines, Valerie L.
• Granted Patent: US 7,038,937 B2
• Time in Patent Office: Days
• US Class Current: 365/230.60
• CPC Class Codes: G11C 11/4085 Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Abstract

A circuit which accurately controls the word line (pass transistor gate) driving voltage to a voltage which is both controlled and is not significantly greater than is needed to drive the word line. The elements of the present invention eliminate the need for a double-boot-strapping circuit, and ensure that no voltages exceed that necessary to fully turn on a memory cell access transistor. Accordingly, voltages in excess of that which would reduce reliability are avoided, and accurate driving voltages are obtained. A DRAM is comprised of word lines, memory cells having enable inputs connected to the word lines, apparatus for receiving word line selecting signals at first logic levels V_ss and V_dd, and for providing a select signal at levels V_ss and V_dd, a high voltage supply source V_pp which is higher in voltage than V_dd, circuit for translating the select signals at levels V_ss and V_dd to levels V_ss and V_pp and for applying it directly to the word lines for application to the enable inputs whereby an above V_dd voltage level word line is achieved without the use of double boot-strap circuits.

Claims

1. A random access memory comprising:

a controlled high voltage supply;

word lines;

memory cells, each comprising a charge storage capacitor and a pass transistor for storing a logic level on the storage capacitor, the pass transistor having an enable input connected to a word line;

word line selection circuits, each selection circuit comprising;

a pair of cross-coupled transistors coupled drain-to-gate at respective control nodes and having respective sources coupled to the controlled high voltage supply;

a first pull-down transistor coupled to one of the control nodes and gated by a word line select signal; and

a second pull-down transistor connected in parallel with the first pull-down transistor to said one of the control nodes, the gate of the second pull-down transistor being coupled to the other control node.