Method and system for configuring fibre channel ports

• US 20050018650A1
• Filed: 07/20/2004
• Published: 01/27/2005
• Est. Priority Date: 07/21/2003
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: QLogic Corporation (Marvell Technology Group Limited)
• Inventors: Dropps, Frank R., Papenfuss, Gary M., Kohlwey, Ernest G.
• Granted Patent: US 7,558,281 B2
• Time in Patent Office: Days
• US Class Current: 370/351
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: H04L 49/101 using crossbar or matrix
• CPC Class Codes: H04L 49/357 Fibre channel switches
• CPC Class Codes: H04L 49/65 Re-configuration of fast packet switches

Abstract

A fibre channel switch element for routing fibre channel frame is provided. The switch element includes a fibre channel port that can be configured to support plural data transfer rates. The data transfer rate may be 1 G, 2 G, 4 G, 8 G or 10 G. The switch element includes a clock configuration module for providing a clock signal that is based on the data transfer rate. A receive segment of the fibre channel port sends a signal to a transmit segment to avoid an under flow condition. The receive segment also waits for a certain frame length after a fibre channel frame is written and before the fibre channel frame is read, depending upon a data transfer rate of a source port. Multiple lanes may be configured as a single 10 G multi lane port or as multiple individual ports.

Claims

1. A fibre channel switch element for routing fibre channel frames, comprising:

a fibre channel port that can be configured to support plural data transfer rates.

2. The switch element of claim 1, wherein the data transfer rate is 1 gigabyte per second.

3. The switch element of claim 1, wherein the data transfer rate is 2 gigabyte per second.

4. The switch element of claim 1, wherein the data transfer rate is 4 gigabyte per second.

5. The switch element of claim 1, wherein the data transfer rate is 8 gigabyte per second.

6. The switch element of claim 1, wherein the data transfer rate is 10 gigabyte per second.

7. The switch element of claim 1, wherein the switch element includes a clock configuration module for providing a clock signal that is based on the data transfer rate.

8. The switch element of claim 1, wherein a receive segment of the fibre channel port sends a signal to a transmit segment to avoid an under flow condition.

9. The switch element of claim 8, wherein a receive segment waits for a certain frame length after a fibre channel frame is written and before the fibre channel frame is read, depending upon a data transfer rate of a source port.

10. The switch element of claim 1, wherein multiple lanes may be configured as a single 10 G multi lane port or as multiple individual ports.

11. The switch element of claim 1, wherein transmit and receive pipelines may be shared between all port speeds.

12. The switch element of claim 1, wherein transmit and receive pipelines may be separate for each port speed or shared between some ports but not shared by all ports.

13. The switch element of claim 1, wherein a receive buffer is shared for multiple lanes when configured to operate with a multi-rate port.

14. The switch element of claim 1, wherein a receive buffer is used for each lane when a port is configured to operate at different rates.

15. The switch element of claim 1, wherein each lane configured as individual independent port may operate at different rates independently.

16. The switch element of claim 1, wherein a port can auto-negotiate between all port rates.

17. The switch element of claim 16, wherein switch element firmware auto-negotiates between different rates.

18. The switch element of claim 16, wherein auto-negotiation is hardware based.