Method for an integrated circuit contact

• US 20050020090A1
• Filed: 08/19/2004
• Published: 01/27/2005
• Est. Priority Date: 07/28/1992
• Status: Active Grant

• Current Assignee: Round Rock Research LLC
• Original Assignee: Charles H. Dennison, Trung T. Doan
• Inventors: Dennison, Charles H., Doan, Trung T.
• Granted Patent: US 7,282,447 B2
• Time in Patent Office: Days
• US Class Current: 438/736
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/76808 involving intermediate temporary filling with material
• CPC Class Codes: H01L 21/76829 characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
• CPC Class Codes: Y10S 438/95 Multilayer mask including nonradiation sensitive layer
• CPC Class Codes: Y10S 438/97 Specified etch stop material

Abstract

A process for forming vertical contacts in the manufacture of integrated circuits and devices. The process eliminates the need for precise mask alignment and allows the etch of the contact hole to be controlled independent of the etch of the interconnect trough. The process including forming an insulating layer on the surface of a substrate; forming an etch stop layer on the surface of the insulating layer; forming an opening in the etch stop layer; etching to a first depth through the opening in the etch stop layer and into the insulating layer to form an interconnect trough; forming a photoresist mask on the surface of the etch stop layer and in the trough; and continuing to etch through the insulating layer until reaching the surface of the substrate to form a contact hole. The process may be repeated during the formation of multilevel metal integrated circuits.

Claims

1. A control method for an etching process, comprising:

using a first resist mask to pattern an etch stop during said etching process;

using said first resist mask to pattern an insulation layer during said etching process; and

using said etch stop and a second resist mask to further pattern said insulation layer during said etching process.

2. The method in claim 1, wherein:

said using a first resist mask to pattern an etch stop comprises using said first resist mask during a first etch step;

said using said first resist mask to pattern an insulation layer comprises using said first resist mask during a second etch step; and

said using said etch stop and a second resist mask comprises using said etch stop and said second resist mask during a third etch step.

3. The method in claim 2, wherein said using said etch stop and said second resist mask during a third etch step comprises using said etch stop and said second resist mask during a reactive ion etch.

4. A processing method for a semiconductor circuit portion including an insulator, comprising:

providing an etch stop as part of said semiconductor circuit portion, said etch stop overlying said insulator;

patterning said etch stop using a first resist mask;

patterning said insulator using said first resist mask; and

patterning said insulator with said etch stop and a second resist mask.

5. The method in claim 4, wherein said providing an etch stop as part of said semiconductor circuit portion comprises providing said etch stop as a permanent part of said semiconductor circuit portion.

6. A method for controlling an etching process, comprising:

using a first resist mask to pattern an etch stop during said etching process;

using said first resist mask to pattern an insulation layer during said etching process; and

using said etch stop and a second resist mask to further pattern said insulation layer during said etching process.

7. The method in claim 6, wherein:

said using a first resist mask to pattern an etch stop comprises using said first resist mask during a first etch step;

said using said first resist mask to pattern an insulation layer comprises using said first resist mask during a second etch step; and

said using said etch stop and a second resist mask comprises using said etch stop and said second resist mask during a third etch step.

8. The method in claim 7, wherein said using said etch stop and said second resist mask during a third etch step comprises using said etch stop and said second resist mask during a reactive ion etch.

9. A method for processing a portion of a semiconductor circuit having an insulator, comprising:

providing an etch stop as part of said semiconductor circuit portion, said etch stop overlying said insulator;

patterning said etch stop using a first resist mask;

patterning said insulator using said first resist mask; and

patterning said insulator with said etch stop and a second resist mask.

10. The method in claim 9, wherein said providing an etch stop as part of said semiconductor circuit portion comprises providing said etch stop as a permanent part of said semiconductor circuit portion.

11. A method for performing an etching process, comprising:

using a first resist mask to pattern an etch stop during said etching process;

using said first resist mask to pattern an insulation layer during said etching process; and

using said etch stop and a second resist mask to further pattern said insulation layer during said etching process.

12. The method in claim 11, wherein:

said using a first resist mask to pattern an etch stop comprises using said first resist mask during a first etch step;

said using said first resist mask to pattern an insulation layer comprises using said first resist mask during a second etch step; and

said using said etch stop and a second resist mask comprises using said etch stop and said second resist mask during a third etch step.

13. The method in claim 12, wherein said using said etch stop and said second resist mask during a third etch step comprises using said etch stop and said second resist mask during a reactive ion etch.

14. A method in a process for controlling the etching of a portion of a semiconductor circuit having an insulator, comprising:

providing an etch stop as part of said semiconductor circuit portion, said etch stop overlying said insulator;

patterning said etch stop using a first resist mask;

patterning said insulator using said first resist mask; and

patterning said insulator with said etch stop and a second resist mask.

15. The method in claim 14, wherein said providing an etch stop as part of said semiconductor circuit portion comprises providing said etch stop as a permanent part of said semiconductor circuit portion.

16. A method for limiting an etching process, comprising:

using a first resist mask to pattern an etch stop during said etching process;

using said first resist mask to pattern an insulation layer during said etching process; and

using said etch stop and a second resist mask to further pattern said insulation layer during said etching process.

17. The method in claim 16, wherein:

said using a first resist mask to pattern an etch stop comprises using said first resist mask during a first etch step;

said using said first resist mask to pattern an insulation layer comprises using said first resist mask during a second etch step; and

said using said etch stop and a second resist mask comprises using said etch stop and said second resist mask during a third etch step.

18. The method in claim 17, wherein said using said etch stop and said second resist mask during a third etch step comprises using said etch stop and said second resist mask during a reactive ion etch.

19. A method for processing a portion of a semiconductor circuit having an insulator for controling the etching thereof, comprising:

providing an etch stop as part of said semiconductor circuit portion, said etch stop overlying said insulator;

patterning said etch stop using a first resist mask;

patterning said insulator using said first resist mask; and

patterning said insulator with said etch stop and a second resist mask.

20. The method in claim 19, wherein said providing an etch stop as part of said semiconductor circuit portion comprises providing said etch stop as a permanent part of said semiconductor circuit portion.